读书笔记 Advanced FPGA（6）Clock Domains

SUMMARY OF KEY POINTS
. Clock synchronization issues are generally not repeatable and will affect
the reliability of the FPGA design.
. Metastability can cause catastrophic failures in the FPGA.
. The phase control technique can be used whenever the period of one clock
is a multiple of the other and when one of the clocks can be controlled by
an internal PLL or DLL.
. Double flopping can be used to resynchronize single-bit signals between
two asynchronous clock domains.
. Timing analysis should ignore the first resynchronization flip-flop and
ensure that the timing between the synchronization flip-flops themselves is
minimized.
. FIFOs can be used when passing multibit signals between asynchronous
clock domains.
. Gray codes can be used to pass multibit counter data between asynchronous
clock domains and are often used inside FIFOs.
. Synchronization registers should be partitioned as independent blocks
outside of the functional modules.
. If at all possible, avoid clock gating. If gating is necessary, keep all gated
clocks inside a dedicated clocks module and separate from the functional
modules.

如果可能的话，避免时钟门控。如果需要门控，则将所有门控时钟保持在专用时钟模块内，并与功能模块分开

良好的时钟域顶层设计习惯