读书笔记 Advanced FPGA（3）Architecting Power

SUMMARY OF KEY POINTS
. Clock control resources such as the clock enable flip-flop input or a global
clock mux should be used in place direct clock gating when they are
available.
. Clock gating is a direct means for reducing dynamic power dissipation but
creates difficulties in implementation and timing analysis.
. Mishandling clock skew can cause catastrophic failures in the FPGA.
. Clock gating can cause hold violations that may or may not be corrected by
the implementation tools.
. To minimize the power dissipation of input devices, minimize the rise and
fall times of the signals that drive the input.
. Always terminate unused input buffers. Never let an FPGA input buffer float.
. Dynamic power dissipation drops off with the square of the core voltage,
but reducing voltage will have a negative impact on performance.
. Dual-edge triggered flip-flops should only be used if they are provided as
primitive elements.

. There is no steady-state current dissipation with a series termination