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最新推荐文章于 2024-09-20 15:52:44 发布

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该文描述了一个用Verilog编写的顺序电路模块，输入包括SW开关、KEY[0]作为时钟和KEY[1]作为控制信号，输出连接到LED灯LEDR。在每个时钟的上升沿，LEDR的状态根据KEY[1]的值和SW的输入更新，形成一种状态转移逻辑。

Taken from 2015 midterm question 5. See also the first part of this question: mt2015_muxdff

Write the Verilog code for this sequential circuit (Submodules are ok, but the top-level must be named top_module). Assume that you are going to implement the circuit on the DE1-SoC board. Connect the R inputs to the SW switches, connect Clock to KEY[0], and L to KEY[1]. Connect the Q outputs to the red lights LEDR.

module top_module (
	input [2:0] SW,      // R
	input [1:0] KEY,     // L and clk
	output [2:0] LEDR);  // Q

    always@(posedge KEY[0])
    begin
        LEDR[2] <= KEY[1] ? SW[2] : LEDR[1] ^ LEDR[2];
        LEDR[1] <= KEY[1] ? SW[1] : LEDR[0];
        LEDR[0] <= KEY[1] ? SW[0] : LEDR[2];
    end

endmodule