在linux中HDL的unit文件架构

在linux系统中，若使用modelsim作为仿真工具，文件的系统架构规范写法为：

建造unit_name文件夹，里面分两个sub-folder：source,modelsim.在source中有两个sub-folder:rtl,tb,分别存放rtl代码与测试的testbench.在modelsim中有simulate_me.sh，vsim.do. simulate_me.sh是script文件，用来设置环境参数与启动仿真,用命令vsim -64 -do vsim.do启动64bit机下modelsim，运行vsim.do；vsim.do用来包含仿真所用到的文件，命令vsim -t fs -novopt sim_top glbl 指定 sim_top为仿真testbench，添加需要观察的波形。

Examp：

simulate_me.sh

#!/bin/bash
export SOURCE_PATH="/axi_wrapper/ddr2-t3/ddr_wrap/source"
export MODELSIM_PATH="/ifn/mns/soft/opt/mentor/questa_10v2/questasim/"
export XILINX_PATH="/ifn/mns/soft/opt/xilinx/vivado_2013v4/Vivado/2013.4/ids_lite/ISE"

# break on error
set -e

# create directory for modelsim libraries
mkdir -p libs

# remove local modelsim.ini file
rm -f modelsim.ini

# create modelsim work library
vlib libs/work

# map work library
vmap work libs/work

#start modelsim and vsim.do
vsim -64 -do vsim.do

vsim.do

set MODELSIM_PATH $::env(MODELSIM_PATH)
set XILINX_PATH $::env(XILINX_PATH)
set SOURCE_PATH $::env(SOURCE_PATH)

catch { vdel -all -lib work }
vlib libs/work
#vlog is for verilog
vlog -quiet  ${XILINX_PATH}/verilog/src/glbl.v 
vlog  -quiet  ${SOURCE_PATH}/rtl/top.v
#vcom is for vhdl,
vcom +acc -quiet -93 \
  ${SOURCE_PATH}/hdl/exam1.vhd \
  ${SOURCE_PATH}/hdl/exam2.vhd
#vlog -sv is special for systemverilog
vlog -sv -quiet  ${SOURCE_PATH}/tb/sim_top.sv

#set and start testbench, top module named sim_top
vsim -t fs -novopt sim_top glbl

#add wave
add wave -noupdate -format Logic -radix hexadecimal sim:/sim_top/my_top/RVALID

run -all