HDLBits 代码输出（一)

最新推荐文章于 2025-06-21 22:08:53 发布

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最新推荐文章于 2025-06-21 22:08:53 发布

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本文链接：https://blog.youkuaiyun.com/buzhiquxiang/article/details/103674109

本文详细介绍了Verilog HDL的基础知识，包括基本逻辑门、向量声明、位操作、模块实例化和过程。特别强调了隐式网络可能导致的错误、位拼接的使用、不同类型的always块以及如何避免创建意外的锁存器。同时讲解了casez和casex在处理不确定状态时的区别。

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(一）Basic
掌握与门、或门、同或门、异或门的符号及其写法即可。
（二）Vector
（1）Vectors must be declared -> type [upper:lower] vector_name;
for example:
wire [7:0] w; // 8-bit wire
reg [4:1] x; // 4-bit reg
output reg [0:0] y; // 1-bit reg that is also an output port (this is still a vector)
input wire [3:-2] z; // 6-bit wire input (negative ranges are allowed)
output [3:0] a; // 4-bit output wire. Type is ‘wire’ unless specified otherwise.
wire [0:7] b; // 8-bit wire where b[0] is the most-significant bit.
注意：The endianness (or, informally, “direction”) of a vector is whether the the least significant bit has a lower index (little-endian, e.g., [3:0]) or a higher index (big-endian, e.g., [0:3]).

（2）Implicit nets ->Implicit nets are always one-bit wires and causes bugs if you had intended to use a vector.
wire [2:0] a, c; // Two vectors
assign a = 3’b101; // a = 101
assign b = a; // b = 1 implicitly-created wire
assign c = b; // c = 001 <-- bug
my_module i1 (d,e); // d and e are implicitly one-bit wide if not declared.
// This could be a bug if the port was intended to be a vector.
尤其要注意这种隐式规则，在不写位宽时，常常会出现错误。
例如： assign z={e[0],f[4:0],2’b11};后两位必须加上位宽。

(3)Unpacked vs. Packed Arrays
reg [7:0] mem [255:0]; // 256 unpacked elements, each of which