Verilog练习：HDLBits笔记1

 一、Getting Started

1、Getting Started

Problem Statement：

Build a circuit with no inputs and one output. That output should always drive 1 (or logic high).

module top_module( output one );

// Insert your code here
    assign one = 1'd1;

endmodule

2、Output Zero

Problem Statement：

Build a circuit with no inputs and one output that outputs a constant 0

module top_module(
    output zero
);// Module body starts after semicolon

endmodule