USTC Verilog OJ Solutions

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已于 2023-04-13 19:48:42 修改 · 3.2k 阅读

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#fpga开发 #Verilog #HDL #risc-v

于 2022-04-21 20:30:53 首次发布

本文介绍了RISC-V单周期CPU的设计，包括内存、寄存器堆、ALU、分支判断模块等核心组件，以及它们在指令执行过程中的作用。通过实例展示了如何处理各种指令，如加法、分支、加载和存储等，并提供了相应的仿真文件编写示例。

科大OJ

其对应的英文版：HDLBits刷题网站

01输出1

module top_module(output one);
    assign one = 1;
endmodule

02输出0

module top_module(
    output zero
);// Module body starts after semicolon
    assign zero = 0;
endmodule

03wire

module top_module(input in, output out);
    assign out = in;
endmodule

04多个端口的模块

module top_module(
    input a, b, c,
    output w, x, y, z
);
    assign w=a;
    assign x=b;
    assign y=b;
    assign z=c;
endmodule

05非门

module top_module(
    input in,
    output out
);
    assign out=~in;
endmodule

06与门

module top_module(
    input a, b,
    output out
);
    assign out=a & b;
endmodule

07或非门

module top_module(
    input a, b,
    output out
);
    assign out=!(a | b);
endmodule

08同或门

module top_module(
    input a, b,
    output out
);
    assign out = !(a ^ b);
endmodule

09线网型中间信号

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   
); 
// 请用户在下方编辑代码
	wire a_and_b, c_and_d, or_out;
    assign a_and_b = a&b;
    assign c_and_d = c&d;
    assign or_out = a_and_b | c_and_d;
    assign out = or_out;
    assign out_n = ~or_out;
//用户编辑到此为止
endmodule

10向量

module top_module ( 
    input wire [2:0] vec,
    output wire [2:0] outv,
    output wire o2,
    output wire o1,
    output wire o0);
// Module body starts after module declaration
// 请用户在下方编辑代码
    assign outv[2:0] = vec[2:0];
    assign o0 = vec[0];
    assign o1 = vec[1];
    assign o2 = vec[2];
// 用户编辑到此为止
endmodule

11向量_续1

`default_nettype none     // Disable implicit nets. Reduces some types of bugs.
module top_module( 
    input	wire	[15:0]	in,
    output	wire	[7:0]	out_hi,
    output	wire	[7:0]	out_lo 
);
	// Write your code here
    assign out_hi = in[15:8];
    assign out_lo = in[7:0];
endmodule

12向量_续2

module top_module(
  input [31:0] in,
  output [31:0] out
);
    assign out[31:24] = in[7:0];
    assign out[23:16] = in[15:8];
    assign out[15:8] = in[23:16];
    assign out[7:0] = in[31:24];
endmodule

13位操作

module top_module( 
    input [2:0] a,
    input [2:0] b,
    output [2:0] out_or_bitwise,
    output out_or_logical,
    output [5:0] out_not
);
  // Write your code here
    assign out_not[5:0] = ~({
   
   b[2:0],a[2:0]});
    assign out_or_bitwise = a | b;
    assign out_or_logical = a[0]|a[1]|a[2]|b[0]|b[1]|b[2];
    
endmodule

14位操作

module top_module( 
    input [3:0] in,
    output out_and,
    output out_or,
    output out_xor
);
    /*
    assign out_and = in[0]&in[1]&in[2]&in[3];
    assign out_or = in[0]|in[1]|in[2]|in[3];
    assign out_xor = in[0]^in[1]^in[2]^in[3];
    */
    assign out_and = &in[2:0];
    assign out_or = |in[2:0];
    assign out_xor = ^in[2:0];
    
endmodule

15向量拼接

module top_module (
    input [4:0] a, b, c, d, e, f,
    output [7:0] w, x, y, z );
    // assign { ... } = { ... };
    assign {
   
   w, x, y, z} = {
   
   a, b, c, d, e, f, 2'b11};
endmodule

16向量翻转

module top_module( 
    input [7:0] in,
    output [7:0] out
);
    assign out = {
   
   in[0], in[1], in[2], in[3], in[4], in[5], in[6], in[7]};
endmodule

17复制算子

module top_module (
    input [7:0] in,
    output [31:0] out );//
    assign out = {
   
   {
   
   24{
   
   in[7]}},in[7:0]};
endmodule

18复制算子_2

module top_module (
    input a, b, c, d, e,
    output [24:0] out );//
    // The output is XNOR of two vectors created by 
    // concatenating and replicating the five inputs.
    assign out = ~({
   
    {
   
   5{
   
   a}}, {
   
   5{
   
   b}},{
   
   5{
   
   c}},{
   
   5{
   
   d}}, {
   
   5{
   
   e}}} ^ {
   
    5{
   
   a, b, c, d, e} });
endmodule

19模块例化

module top_module(
  input 	a,
  input 	b,
  output 	out
);
  
// 请用户在下方编辑代码
    mod_a imod_a1(
        .in1(a),
        .in2(b),
        .out(out)
    );
//用户编辑到此为止
endmodule

module mod_a ( 
  input 	in1, 
  input 	in2, 
  output 	out 
);
assign out = in1 & in2;
endmodule

20基于端口位置的实例化

module mod_a(
	output out1, out2,
	input in1,in2,in3,in4);
	assign out1 = in1 & in2 & in3 & in4; 	//这只是一个简单的示例
	assign out2 = in1 | in2 | in3 | in4;	//这只是一个简单的示例
endmodule

module top_module( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);
// 请用户在下方编辑代码
mod_a imod_a1(out1, out2, a, b, c, d);
// 用户编辑到此为止
endmodule

21基于端口名称的实例化

module mod_a (
    output   out1	,
    output   out2	,
    input    in1	,
    input    in2	,
    input    in3	,
    input    in4
);
    assign out1 = in1 & in2 & in3 & in4;    //这只是一个简单的示例
    assign out2 = in1 | in2 | in3 | in4;    //这只是一个简单的示例
endmodule

module top_module ( 
	input	a	,
    input	b	,
    input	c	,
    input	d	,
    output	out1,
    output	out2
);
	//Write your code here
    mod_a imod_a1(
        .out1(out1),
        .out2(out2),
        .in1(a),
        .in2(b),
        .in3(c),
        .in4(d)
    );
endmodule

22多个模块的例化

module my_dff(input clk,input d,output reg q);
	always@(posedge clk)
    	q <= d;
endmodule

module top_module ( input clk, input d, output q );
 // Write your code here
    wire t1, t2;
    my_dff idff1(clk, d, t1);
    my_dff idff2(clk, t1, t2);
    my_dff idff3(clk, t2, q);
endmodule

23模块与向量信号

module my_dff8(
  input clk,
  input [7:0] d,
  output reg [7:0] q
);
	always@(posedge clk)
    	q <= d;
endmodule

module top_module(
  input clk,
  input [7:0] d,
  input [1:0] sel,
  output reg [7:0] q
);
  // Write your code here
    wire [7:0]t1;
    wire [7:0]t2;
    wire [7:0]t3;
    my_dff8 idff8_1(clk, d, t1);
    my_dff8 idff8_2(clk, t1, t2);
    my_dff8 idff8_3(clk, t2, t3);
    
    always @(*) begin
        case(sel)
            2'd0: q <= d;
        	2'd1: q <= t1;
        	2'd2: q <= t2;
        	2'd3: q <= t3;
        endcase
    end       
endmodule

24加法器

module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );
	assign {
   
   cout,sum} = a + b + cin;
endmodule

module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
  wire c;
    add16 iadd16_1(.a(a[15:0]), .b(b[15:0]), .cin(0), .sum(sum[15:0]), .cout(c));
    add16 iadd16_2(.a(a[31:16]), .b(b[31:16]), .cin(c), .sum(sum[31:16]), .cout());
endmodule

25多层次例化加法器

module add1 ( input a, input b, input cin,   output sum, output cout );
// Full adder module here
    assign sum = a ^ b ^ cin;
    assign cout = (a&b)|(a&cin)|(b&cin);
endmodule

module top_module (
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum    
);//
    wire c;
    add16 a0(.a(a[15:0]), .b(b[15:0]), .cin(1'b0), .sum(sum[15:0]), .cout(c));
    add16 a1(.a(a[31:16]), .b(b[31:16]), .cin(c), .sum(sum[31:16]), .cout());
endmodule

26进位选择加法器

module add16 ( 
	input[15:0] a, 
    input[15:0] b, 
    input cin, 
    output[15:0] sum, 
    output cout 
);
	assign {
   
   cout,sum} = a + b + cin;
endmodule

module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire [15