** Error: (vlog-7) Failed to open design unit file “ “ in read mode.

利用Modelsim软件仿真时，我使用.do脚本编译FPGA的文件。但是，遇到了如下错误警告，通过尝试，发现了问题。

# ** Warning: (vlog-159) Mode option -64 is not supported in this context and will be ignored.
# Model Technology ModelSim SE-64 vlog 2019.2 Compiler 2019.04 Apr 17 2019
# Start time: 16:45:40 on Nov 01,2023
# vlog -64 -incr -work xil_defaultlib "+incdir+./" "+incdir+../sim_src/ddr3_sdram_tb/" ../sim_src/fpga_syn_top_tb.sv   
# -- Skipping module fpga_syn_top_tb
# ** Error: (vlog-7) Failed to open design unit file " " in read mode.
# No such file or directory. (errno = ENOENT)
# End time: 16:45:40 on Nov 01,2023, Elapsed time: 0:00:00
# Errors: 1, Warnings: 1
# child process exited abnormally

问题的原因是如下，“\”后不能有空格；删除空格后，就可以了。