LATTICE DDR3 Design tips

LATTICE DDR3 Design tips

1、Why does ispLEVER & Lattice Diamond Place and Route generate errors when I assign DDR3 Address or Command output signals to DQS pins?
For DDR3, the Address & Command outputs are generated using the DDR registers(ODDRXD1 modules). The DQSP and DQSN pins do not support DDR registers hence the error. These outputs will need to be assigned to non-DQS pins.Please see section “DDR3 Pinout Guidelines” in Technical Note TN1180 for all the DDR3 pinout rules.

2、Can the CLKP/CLKN outputs of the DDR3 memory controller be placed on the top side of the LatticeECP3 device?
The DDR3 (Double Data Rate - 3) CLKP/CLKN pads use a generic output DDR function (ODDR). The recommendation is to place the CLKP/CLKN outputs on the same side that the DQ and DQS pads are located. This is because the top side pads are not for the high-speed DDR function that can safely meet the DDR3 performance requirement on the LatticeECP3 device. Note that DDR3 DQ/DQS pads can be located only on the left or right side. Therefore, it is recommended that you locate the CLKP/CLKN pads on the left or right side depending on where the DQ/DQS pads are located.See TN1180 LatticeECP3 High-Speed I/O Interface, DDR3 Pinout Guidelines section for more general pinout guidelines.

3、Does the Lattice DDR3 IP core automatically perform the ZQ calibaration and Auto Refresh commands during or after the initialization?
During initializationThe DDR3 controller IP core performs both ZQ calibration long (ZQCL) and auto refresh commands during the DDR3 initialization process. It is a requirement defined by JEDEC DDR3 specification. After initializationAfter the initialization process is completed, the auto-refresh is still performed by the core at the interval configured with the tREFI parameter (Refresh interval time) and the number for the Auto-Refresh command burst (Auto Refresh Burst
Count). Therefore, there is no need for you to do anything for the auto refresh.
As for the ZQ calibration, it is an optional process for you to perform the calibration on demand basis. The DDR3 IP core does not provide auto-periodic ZQ calibration once the initialization process is completed. However, the core provides two user commands, ZQ_LNG (ZQ calibration long) and ZQ_SHRT (ZQ calibration short), to calibrate the DDR3 memory as needed. Since this process may impact the throughput and it is not a requirement once the initialization is completed, the ZQ calibration control will only run if implemented by the user.

4、Can I connect both the “mem_rst_n” and “rst_n” signals in the Lattice DDR3 IP core together to a system reset to meet the JEDEC initialization requirement?
The “rsn_n” signal resets both the DDR3 memory controller and the DDR3 memory devices while the “mem_rst_n” signal resets only the DDR3 memory devices. The JEDEC specification has two different cases of reset initialization. Power-up reset initialization: The memory reset needs to be asserted at least 200us with stable power. In this case, there is no need for the memory clock (CK) to be stable according to JEDEC. Since the DDR3 IP core does not provide a wait counter for this requirement, it is user’s responsibility to ensure to meet the required reset duration. 2. Reset assertion with stable power: Once the reset is asserted, according to JEDEC, it is required to remain below 0.2 * VDD for minimum 100ns. The Lattice DDR3 IP core supports this requirement. When you assert a reset pulse which is shorter than 100ns on mem_rst_n, the core will ensure it is asserted at least for 100ns.With these conditions, you can connect your system reset to both “rst_n” and “mem_rst_n” if your system reset duration is guaranteed longer than 200us after power becomes stable. If not, you will need to keep the mem_rst_n signal asserted at least for 200us with stable power to follow the JEDEC memory power-on reset requirement.

5、How can I configure the DDR3 memory clock to double the reference frequency (1:2:1 ratio) instead of multiple of 4x (1:4:2)?
The CSM (Clock Synchronization Module) module of the DDR3 memory controller ipcore multiplies the input reference clock frequency four times for the DDR3 bus operations and two times for the local bus operations. This means that the DDR3 IP core uses 1:4:2 ratio (input clock vs. DDR3 clock vs. local clock). If you use a DDR3 IP core version 1.2 or later (or any DDR3 PHY IP core version), you can manually change this ratio by following the steps below:
1. Open the ddr3_pll.v file inside the models folder using a text editor. It is located under ddr_p_eval\models\ecp3.
2. Launch IPexpress and select “PLL”. Configure the PLL with the options shown in the ddr3_pll.v file. Make sure you assign the module name to “ddr3_pll”.
3. Change the input and output clock frequencies to your desired values. If you want to use 150MHz as DDR3 reference clock input and DDR3 memory clock is 300MHz, you can set CLKOP=300.0MHz CLKOK=150.0MHz. Click “Calculate” then “Generate”.
4. If the generated PLL has more input or output pins than the original ddr_pll.v, you may need to manually edit the generated file so that the module can be properly instantiated. Use the original ddr3_pll.v file.
5. As an alternative, you can edit the original ddr_pll.v file with the divider values and parameters from the generated PLL module. You can select whichever way you feel more convenient.

6、I cannot assign the DDR3 memory clock (CK) pads to Bank 1 during the DDR3 core generation when the left side of a LatticeECP3 device is selected for a DDR3 interface running at 300MHz. How can I use the pins in Bank 1 for CK?
LatticeECP3 has the following pinout guideline for a DDR3 CK pair assignment (See TN1180 DDR3 Pinout Guidelines section.):
It’s recommended that the CK pads are located on the same side as data pads when the DDR3 bus is running at high speed (400MHz).
At a lower operating speed such as 333 or 300MHz, however, CK can be located on either the same side as data pads or a top-side bank. In this example, both Bank 0 and Bank 1 are legal locations to accommodate a CK pair if your target speed is 300MHz or 333MHz. The reason why the DDR3 IP core allows only Bank 0 in this case is because assigning the CK pad to Bank 1 is generally not practical in terms of pin resource allocation and static timing achievement. If the CK pads are located on the other side of the top bank, for example, it may cause a static timing failure if the internal routing delays are excessive. Although a pair in Bank 1 can be used as CK, the DDR3 IP core does not encourage you to use it due to this reason.
If you have to use a pair in Bank 1, you can generate a DDR3 IP core with CK assigned to Bank 0 first. Then, you can simply update the target bank for the CK pair from Bank 0 to Bank 1 in the preference file (.LPF) as shown below.
DEFINE PORT GROUP “EM_DDR_CLK_GRP” “em_ddr_clk_*” ;IOBUF GROUP “EM_DDR_CLK_GRP” IO_TYPE=SSTL15D BANK=1 ;
You will need to make sure not to violate the static timing requirement.

7、What should I do with the LatticeECP3 DDR3 memory interface VTT termination?
Only external VTT termination should be used for LatticeECP3 DDR3. Use of LatticeECP3’s internal on-die termina