报错
[Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I0, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: adc_datareceive_inst/FIFO_adc240bit_inst/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_4.
原因
有个LUT2 cell的IO脚未连接。
adc_datareceive_inst/FIFO_adc240bit_inst/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_4.
解决办法
根据提供的层级在原理图中查找。
双击层级时观察是否有端口未连接,最后的LU2发现I0有连接,反查I0的上一级,一直查到未连接处。