Edgecapture的收获

题目：
For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. “Capture” means that the output will remain 1 until the register is reset (synchronous reset).

Each output bit behaves like a SR flip-flop: The output bit should be set (to 1) the cycle after a 1 to 0 transition occurs. The output bit should be reset (to 0) at the positive clock edge when reset is high. If both of the above events occur at the same time, reset has precedence. In the last 4 cycles of the example waveform below, the ‘reset’ event occurs one cycle earlier than the ‘set’ event, so there is no conflict here.

In the example waveform below, reset, in[1] and out[1] are shown again separately for clarity.

我的代码1：

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);

    reg [31:0] in_reg = 32'd0;
    always@(posedge clk) begin
        in_reg <= in;
    end
    reg [31:0] inplusin_reg = 32'd0;
    
    
    integer i;
        always@(posedge clk) begin
            for (i = 0; i < 32; i = i+1) begin:find_1_0
                if(reset)
                    inplusin_reg <= 32'd0;
                else if(in_reg[i]&~in[i]&!reset)
                     inplusin_reg[i] <= 1;
                else
                     inplusin_reg[i] <= inplusin_reg[i];
                end
        end
        assign out = inplusin_reg;
endmodule

运行结果：

我的代码2

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);

    reg [31:0] in_reg = 32'd0;
    always@(posedge clk) begin
        in_reg <= in;
    end
    reg [31:0] inplusin_reg = 32'd0;
    
    
    genvar i;
    generate
            for (i = 0; i < 32; i = i+1) begin:find_1_0
                always@(posedge clk) begin
                	if(reset)
                        inplusin_reg[i] <= 32'd0;
                	else if(in_reg[i]&~in[i]&!reset)
                     	inplusin_reg[i] <= 1;
                	else
                     	inplusin_reg[i] <= inplusin_reg[i];
                	end
        	end
    endgenerate
        assign out = inplusin_reg;
endmodule

收获：
1.reg类型的变量要记得赋初值，赋初值的时候要注意这个值是怎么变化的，可参考本篇博客
2.这里for与generate for 运行都正确，但有时候有些问题，具体规律还没有发现