阿里平头哥无剑100SOCwujian100挂UART外设之①将无剑100下载到gensys开发板

MNVCAT

已于 2022-03-11 14:41:43 修改

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文章标签： fpga开发

于 2022-03-10 11:41:26 首次发布

本文链接：https://blog.youkuaiyun.com/weixin_42312623/article/details/123397516

版权

本文档详细记录了将无剑100 SOC成功连接到gensys开发板并解决UART无串口输出问题的过程。主要涉及了时钟修改、XDC文件调整，以及对开发板硬件接口的配置，包括UART、GPIO等。通过这些步骤，实现了项目的基础搭建。

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一、前言

组里的布置的任务，给大项目的推进打个小小的基础。经过上学期一个月和这学期开学几周，终于解决。其实真正用在挂UART的时间不多，大部分时间都用在如何把无剑100SOC下载到gensys开发板和解决为什么无剑100自带的UART没串口输出的问题。

二、改时钟

找到无剑100源码，下到gensys2开发板，主要一个问题：gensys2的时钟是差分，无剑100的是单端。解决办法，就是在IP核中搜一个clk分频，在输入设置中，将输入时钟设置为差分。之后在顶层文件中调用它，端口名一一对应。具体操作步骤见下图。

clk_wiz_0 u_clk_wiz_0
 (
  // Clock out ports
  .clk_out1(PIN_EHS),
  // Status and control signals
  .resetn(PAD_MCURST),
 // Clock in ports
  .clk_in1_p(clk_p),
  .clk_in1_n(clk_n)
 );

三、修改XDC文件

略，这个根据慕课上的教程提供的nexysvideo开发板的XDC文件，照着修改就行。gensys2核nexysvideo是一个公司的。我的XDC文件如下。

#### This file is a general .xdc for the Genesys 2 Rev. H
#### To use it in a project:
#### - uncomment the lines corresponding to used pins
#### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project

## Clock Signal
## Clock Signal
set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVDS} [get_ports clk_n]
set_property -dict {PACKAGE_PIN AD12 IOSTANDARD LVDS} [get_ports clk_p]
#create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk_p]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets PAD_JTAG_TCLK]

## Buttons
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS12} [get_ports PAD_GPIO_8]
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS12} [get_ports PAD_GPIO_9]
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS12} [get_ports PAD_GPIO_10]
set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVCMOS12} [get_ports PAD_GPIO_11]
set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS12} [get_ports PAD_GPIO_12]
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports PAD_MCURST]

## LEDs
set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS33} [get_ports PAD_USI0_NSS]
set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports PAD_GPIO_0]
set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVCMOS33} [get_ports PAD_GPIO_1]
set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVCMOS33} [get_ports PAD_GPIO_2]
set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports POUT_EHS]
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS33} [get_ports PAD_USI0_SD1]
set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS33} [get_ports PAD_PWM_CH9]
set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS33} [get_ports PAD_USI2_NSS]

## Switches
set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS12} [get_ports PAD_PWM_CH10]
set_property -dict {PACKAGE_PIN G25 IOSTANDARD LVCMOS12} [get_ports PAD_PWM_CH11]
set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS12} [get_ports PAD_PWM_CH0]
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS12} [get_ports PAD_PWM_CH1]
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS12} [get_ports PAD_PWM_CH2]
set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS12} [get_ports PAD_GPIO_31]
set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS33} [get_ports PAD_GPIO_30]
set_property -dict {PACKAGE_PIN P27 IOSTANDARD LVCMOS33} [get_ports PAD_GPIO_29]

## USB HIDs For Both Mouse and Keyboard
#set_property -dict { PACKAGE_PIN AD23  IOSTANDARD LVCMOS33  PULLUP true } [get_ports { ps2_clk_0 }]; #IO_L12P_T1_MRCC_12 Sch=ps2_clk[0]
#set_property -dict { PACKAGE_PIN AE20  IOSTANDARD LVCMOS33  PULLUP true } [get_ports { ps2_data_0 }]; #IO_25_12 Sch=ps2_data[0]

## UART
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS33} [get_ports PAD_USI0_SD0]
set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports PAD_USI0_SCLK]


## SD Card
set_property -dict {PACKAGE_PIN P28 IOSTANDARD LVCMOS33} [get_ports PAD_GPIO_18]
set_property -dict {PACKAGE_PIN R29 IOSTANDARD LVCMOS33} [get_ports PAD_GPIO_5]
set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS33} [get_ports PAD_GPIO_7]
#set_property -dict { PACKAGE_PIN R30   IOSTANDARD LVCMOS33 } [get_ports { sd_d[1] }]; #IO_L9P_T1_DQS_14 Sch=sd_dat[1]
#set_property -dict { PACKAGE_PIN P29   IOSTANDARD LVCMOS33 } [get_ports { sd_d[2] }]; #IO_L7P_T1_D09_14 Sch=sd_dat[2]
set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVCMOS33} [get_ports PAD_GPIO_19]
set_property -dict {PACKAGE_PIN AE24 IOSTANDARD LVCMOS33} [get_ports PAD_GPIO_20]
set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS33} [get_ports PAD_GPIO_6]

## Audio Codec
#set_property -dict { PACKAGE_PIN AH19  IOSTANDARD LVCMOS18 } [get_ports { aud_adc_sdata }]; #IO_L8N_T1_32 Sch=aud_adc_sdata
#set_property -dict { PACKAGE_PIN AD19  IOSTANDARD LVCMOS18 } [get_ports { aud_adr[0] }]; #IO_L10P_T1_32 Sch=aud_adr[0]
#set_property -dict { PACKAGE_PIN AG19  IOSTANDARD LVCMOS18 } [get_ports { aud_adr[1] }]; #IO_L8P_T1_32 Sch=aud_adr[1]
#set_property -dict { PACKAGE_PIN AG18  IOSTANDARD LVCMOS18 } [get_ports { aud_bclk }]; #IO_L11N_T1_SRCC_32 Sch=aud_bclk
#set_property -dict { PACKAGE_PIN AJ19  IOSTANDARD LVCMOS18 } [get_ports { aud_dac_sdata }]; #IO_L7P_T1_32 Sch=aud_dac_sdata
#set_property -dict { PACKAGE_PIN AJ18  IOSTANDARD LVCMOS18 } [get_ports { aud_lrclk }]; #IO_L9P_T1_DQS_32 Sch=aud_lrclk
#set_property -dict { PACKAGE_PIN AK19  IOSTANDARD LVCMOS18 } [get_ports { aud_mclk }]; #IO_L7N_T1_32 Sch=aud_mclk
#set_property -dict { PACKAGE_PIN AE19  IOSTANDARD LVCMOS18 } [get_ports { aud_scl }]; #IO_L10N_T1_32 Sch=aud_scl
#set_property -dict { PACKAGE_PIN AF18  IOSTANDARD LVCMOS18 } [get_ports { aud_sda }]; #IO_L11P_T1_SRCC_32 Sch=aud_sda

## Ethernet
#set_property -dict { PACKAGE_PIN AK16  IOSTANDARD LVCMOS18 } [get_ports { eth_int_b }]; #IO_L1P_T0_32 Sch=eth_intb
#set_property -dict { PACKAGE_PIN AF12  IOSTANDARD LVCMOS15 } [get_ports { eth_mdc }]; #IO_L23P_T3_33 Sch=eth_mdc
#set_property -dict { PACKAGE_PIN AG12  IOSTANDARD LVCMOS15 } [get_ports { eth_mdio }]; #IO_L23N_T3_33 Sch=eth_mdio
#set_property -dict { PACKAGE_PIN AH24  IOSTANDARD LVCMOS33 } [get_ports { ETH_PHYRST_N }]; #IO_L14N_T2_SRCC_12 Sch=eth_phyrst_n
#set_property -dict { PACKAGE_PIN AK15  IOSTANDARD LVCMOS18 } [get_ports { eth_pme_b }]; #IO_L1N_T0_32 Sch=eth_pmeb
#set_property -dict { PACKAGE_PIN AG10  IOSTANDARD LVCMOS15 } [get_ports { eth_rxck }]; #IO_L13P_T2_MRCC_33 Sch=eth_rx_clk
#set_property -dict { PACKAGE_PIN AH11  IOSTANDARD LVCMOS15 } [get_ports { eth_rxctl }]; #IO_L18P_T2_33 Sch=eth_rx_ctl
#set_property -dict { PACKAGE_PIN AJ14  IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_33 Sch=eth_rx_d[0]
#set_property -dict { PACKAGE_PIN AH14  IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[1] }]; #IO_L21P_T3_DQS_33 Sch=eth_rx_d[1]
#set_property -dict { PACKAGE_PIN AK13  IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[2] }]; #IO_L20N_T3_33 Sch=eth_rx_d[2]
#set_property -dict { PACKAGE_PIN AJ13  IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[3] }]; #IO_L22P_T3_33 Sch=eth_rx_d[3]
#set_property -dict { PACKAGE_PIN AE10  IOSTANDARD LVCMOS15 } [get_ports { eth_txck }]; #IO_L14P_T2_SRCC_33 Sch=eth_tx_clk
#set_property -dict { PACKAGE_PIN AJ12  IOSTANDARD LVCMOS15 } [get_ports { eth_txd[0] }]; #IO_L22N_T3_33 Sch=eth_tx_d[0]
#set_property -dict { PACKAGE_PIN AK11  IOSTANDARD LVCMOS15 } [get_ports { eth_txd[1] }]; #IO_L17P_T2_33 Sch=eth_tx_d[1]
#set_property -dict { PACKAGE_PIN AJ11  IOSTANDARD LVCMOS15 } [get_ports { eth_txd[2] }]; #IO_L18N_T2_33 Sch=eth_tx_d[2]
#set_property -dict { PACKAGE_PIN AK10  IOSTANDARD LVCMOS15 } [get_ports { eth_txd[3] }]; #IO_L17N_T2_33 Sch=eth_tx_d[3]
#set_property -dict { PACKAGE_PIN AK14  IOSTANDARD LVCMOS15 } [get_ports { ETH_TX_EN }]; #IO_L20P_T3_33 Sch=eth_tx_en

## VGA Connector
#set_property -dict { PACKAGE_PIN AH20  IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L22N_T3_12 Sch=vga_b[3]
#set_property -dict { PACKAGE_PIN AG20  IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L22P_T3_12 Sch=vga_b[4]
#set_property -dict { PACKAGE_PIN AF21  IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L19N_T3_VREF_12 Sch=vga_b[5]
#set_property -dict { PACKAGE_PIN AK20  IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L24P_T3_12 Sch=vga_b[6]
#set_property -dict { PACKAGE_PIN AG22  IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L20P_T3_12 Sch=vga_b[7]

#set_property -dict { PACKAGE_PIN AJ23  IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L21N_T3_DQS_12 Sch=vga_g[2]
#set_property -dict { PACKAGE_PIN AJ22  IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L21P_T3_DQS_12 Sch=vga_g[3]
#set_property -dict { PACKAGE_PIN AH22  IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L20N_T3_12 Sch=vga_g[4]
#set_property -dict { PACKAGE_PIN AK21  IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L24N_T3_12 Sch=vga_g[5]
#set_property -dict { PACKAGE_PIN AJ21  IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L23N_T3_12 Sch=vga_g[6]
#set_property -dict { PACKAGE_PIN AK23  IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L17P_T2_12 Sch=vga_g[7]

#set_property -dict { PACKAGE_PIN AK25  IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L15N_T2_DQS_12 Sch=vga_r[3]
#set_property -dict { PACKAGE_PIN AG25  IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO