FPGA学习之流水灯的实现

最新推荐文章于 2024-07-26 22:24:19 发布

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最新推荐文章于 2024-07-26 22:24:19 发布

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CC 4.0 BY-SA版权

原文链接：http://www.cnblogs.com/zxqwolf/archive/2013/03/03/2941682.html

本文分享了一个简单的流水灯实验代码，采用Verilog HDL语言编写，实现了LED灯的流水效果。文章详细展示了模块定义、状态机设计及信号赋值等关键部分。

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当然作为入门实验的流水灯实验是很简单的。基本没有什么可操作性

但是为了完整性,我也试着写了一个简单的。

module ledflow(
input clk,
input rst_n,

output [7:0] leds
);

reg [7:0]leds_r;
assign leds = leds_r;

reg [24:0] clk_cnt_r;
reg en_leds_r;
reg [7:0]ledstate;
parameter leddata0 = 8'b1111_1110,
                leddata1 = 8'b1111_1101,
      leddata2 = 8'b1111_1011,
      leddata3 = 8'b1111_0111,
      leddata4 = 8'b1110_1111,
      leddata5 = 8'b1101_1111,
      leddata6 = 8'b1011_1111,
      leddata7 = 8'b0111_1111;
/////////////17D7840 = 25M ////////////////////////////////
always @ (posedge clk or negedge rst_n)
if(!rst_n)
   clk_cnt_r <= 25'd0;
else
begin
   clk_cnt_r <= clk_cnt_r + 1'b1;
   case(clk_cnt_r)
   25'h17D7840 : begin clk_cnt_r <= 25'd0; en_leds_r <= 1'b1; end
   default           : en_leds_r <= 1'b0;
endcase
end

always @ (posedge clk or negedge rst_n)
if(!rst_n)
    begin
    leds_r <= 8'b0000_0000;
  ledstate <= leddata0;
end
else
   begin
    if(en_leds_r)
     begin
     case(ledstate)
     leddata0 : begin leds_r <= leddata0; ledstate <= leddata1; end
   leddata1 : begin leds_r <= leddata1; ledstate <= leddata2; end
   leddata2 : begin leds_r <= leddata2; ledstate <= leddata3; end
   leddata3 : begin leds_r <= leddata3; ledstate <= leddata4; end
   leddata4 : begin leds_r <= leddata4; ledstate <= leddata5; end
   leddata5 : begin leds_r <= leddata5; ledstate <= leddata6; end
   leddata6 : begin leds_r <= leddata6; ledstate <= leddata7; end
   leddata7 : begin leds_r <= leddata7; ledstate <= leddata0; end
   default   : begin leds_r <= 8'b11111111;ledstate<=leddata0;end
  endcase
   end
end
endmodule