基于FPGA的流水灯实现

最新推荐文章于 2023-03-15 22:34:29 发布

原创最新推荐文章于 2023-03-15 22:34:29 发布 · 1k 阅读

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#FPGA #流水灯

忙了一阵子，今天终于有空闲下来玩玩已经沉睡已久的开发板。还记得上次玩FPGA是在两年之前，现在用Verilog硬件描述有些许生疏了。为了再次捡起以前的技术，决定从最基础学起。废话不多说，贴出Verilog实现流水灯的代码。

方法一：

module run_led(
clk_i,
rstn_i,
led_o
);

input clk_i;
input rstn_i;
output [3:0]led_o;

reg [3:0]led_r;

reg [25:0]cnt;

reg [1:0]state;

always@(posedge clk_i or negedge rstn_i)begin
if(!rstn_i)
   cnt <= 26'd0;
else if(cnt == 26'd50000000)
   cnt <= 26'd0;
else
   cnt <= cnt + 1'd1;
end

always@(posedge clk_i or negedge rstn_i)begin
if(!rstn_i)
state <= 2'd0;
else if(cnt == 26'd50000000)
state = state + 1'b1;
end

always@(posedge clk_i or negedge rstn_i)begin
if(!rstn_i)
   led_r <= 4'b1111;
   else
   case(state)
       2'd0: led_r <= 4'b1000;
       2'd1: led_r <= 4'b0100;
       2'd2: led_r <= 4'b0010;
       2'd3: led_r <= 4'b0001;
       endcase
end

assign led_o = led_r;

endmodule

方法二：

module run_led(
clk_i,
rstn_i,
led_o
);

input clk_i;
input rstn_i;

output [3:0]led_o;

reg [25:0]cnt;

reg [3:0]led_r;

always@(posedge clk_i or negedge rstn_i)begin
if(!rstn_i)
   cnt <= 26'd0;
else if(cnt == 26'd50000000)
   cnt <= 26'd0;
else
   cnt <= cnt + 1'd1;
end

always@(posedge clk_i or negedge rstn_i)begin
if(!rstn_i)
   led_r <= 4'b0001;
else if(cnt == 26'd50000000)begin
   if(led_r == 4'b1000)led_r <= 4'b0001;
   else led_r <= led_r << 1'b1;
   end
end

assign led_o = led_r;

endmodule