时钟分频引起的问题

最新推荐文章于 2023-11-11 10:26:20 发布

seven-soft

最新推荐文章于 2023-11-11 10:26:20 发布

阅读量1.2k

点赞数

CC 4.0 BY-SA版权

分类专栏： FPGA Verilog HDL

本文链接：https://blog.youkuaiyun.com/softn/article/details/51892760

FPGA 同时被 2 个专栏收录

7 篇文章

订阅专栏

Verilog HDL

4 篇文章

订阅专栏

该博客讨论了在时钟分频过程中遇到的时序分析警告，分析了由于clk1us激励代码被视为组合逻辑电路造成的问题。作者提出了一种改进方案，通过引入额外的寄存器和边沿检测信号来避免时序不满足条件，从而解决了这个问题。

摘要生成于 C知道，由 DeepSeek-R1 满血版支持，前往体验 >

代码：

<textarea cols="87" rows="15" name="code" class="c-sharp">reg[31:0] wait_count; reg[31:0] max_wait_count; //times/1us always @(posedge clk1) max_wait_count <= {sendTickH, sendTickL}; reg clk1us; parameter US_COUNT_OF_25M = 12500; reg[15:0] clk1us_count; always @(posedge clk25 or negedge gblnrst) begin if(!gblnrst) begin clk1us_count <= 16'd0; clk1us <= 1'b0; end else begin if(clk1us_count < US_COUNT_OF_25M) clk1us_count <= clk1us_count + 16'd1; else begin clk1us_count <= 16'd0; clk1us <= ~clk1us; end end end always @(posedge clk1us) begin if(fiber_state2 < FIBER_CALC) begin wait_count <= 32'd0; wait_status_ok <= 1'b0; end else begin if(wait_count >= max_wait_count && (fiber_state2 == FIBER_CALC || fiber_state2 == FIBER_FILL)) begin wait_count <= 32'd0; end else begin if(wait_count < max_wait_count) wait_count <= wait_count + 32'd1; else wait_status_ok <= 1'b1; end end end </textarea>

RTL图

STA时序分析工具出现警告时序不满足条件。查看RTL图，发现clk1us激励代码被认为clk25下的组合逻辑电路，最终造成时序不满足条件。后来想到一个办法：

改为：

<textarea cols="87" rows="15" name="code" class="c-sharp">reg[31:0] wait_count; reg[31:0] max_wait_count; //times/1us always @(posedge clk1) max_wait_count <= {sendTickH, sendTickL}; reg clk1us, clk1us_1, clk1us_2; parameter US_COUNT_OF_25M = 12500; reg[15:0] clk1us_count; always @(posedge clk25 or negedge gblnrst) begin if(!gblnrst) begin clk1us_count <= 16'd0; clk1us <= 1'b0; end else begin if(clk1us_count < US_COUNT_OF_25M) clk1us_count <= clk1us_count + 16'd1; else begin clk1us_count <= 16'd0; clk1us <= ~clk1us; end end end always @(posedge clk25) begin clk1us_1 <= clk1us; clk1us_2 <= clk1us_1; end wire clk1us_posedge; assign clk1us_posedge = ~clk1us_2 & clk1us_1; always @(posedge clk25) begin if(fiber_state2 < FIBER_CALC) begin wait_count <= 32'd0; wait_status_ok <= 1'b0; end else begin if(clk1us_posedge) begin if(wait_count >= max_wait_count && (fiber_state2 == FIBER_CALC || fiber_state2 == FIBER_FILL)) begin wait_count <= 32'd0; end else begin if(wait_count < max_wait_count) wait_count <= wait_count + 32'd1; else wait_status_ok <= 1'b1; end end end end </textarea>