牛客网verilog VL32 非整数倍数据位宽转换24to128

最新推荐文章于 2025-05-14 21:29:24 发布

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最新推荐文章于 2025-05-14 21:29:24 发布 · 225 阅读

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#fpga开发

修改了前辈写的很好的代码

`timescale 1ns/1ns

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);
    reg [3:0]   cnt;
    reg [127:0] data_lock;
    
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            cnt <= 0;
        else
			if(cnt<15)begin
				cnt <= ~valid_in? cnt:cnt+1;
			end
			else begin
				cnt <= 0;
			end
            //cnt <= ~valid_in? cnt:cnt+1;
    end
    
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            valid_out <= 0;
        else
            valid_out <= (cnt==5 || cnt==10 || cnt==15)&&valid_in;
    end
    
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            data_lock <= 0;
        else
            data_lock <= valid_in? {data_lock[103:0], data_in}: data_lock;
    end
    
    always@(posedge clk or negedge rst