VerilogHDL 状态机

题目1

        This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.

        This exercise is the same as fsm1s, but using asynchronous reset.

module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);//  

    parameter A=0, B=1; 
    reg state, next_state;


    always @(*) begin    // This is a combinational always block
        // State transition logic
        case(state)
            A:begin
                if(in == 1'b1)
                    next_state <= A;
                else
                    next_state <= B;
            	end
           B:begin
               if(in == 1'b1)
                   next_state <= B;
               else
                   next_state <= A;
              end
        endcase                  

    end

    always @(posedge clk, posedge areset) begin    // This is a sequential always block
        // State flip-flops with asynchronous reset
        if(areset)
            state <= B;
        else
            state <= next_state;
    end

    // Output logic
    // assign out = (state == ...);
            assign out = (state == B);
endmodule

方法2

    always@(*)begin
        case(state)
            B:begin
                out = 1'b1;
            end
            A:begin
                out = 1'b0;
            end
        endcase
    end

方法3

    always@(posedge clk or posedge areset)begin
        if(areset)begin
            out <= 1'b1;
        end
        else if(next_state == B)begin
            out <= 1'b1;
        end
        else begin
            out <= 1'b0;
        end
    end

方法4 

    always@(*)begin 
        if(state == B)begin
            out = 1'b1;
        end
        else begin
            out = 1'b0;
        end
    end

题目2

        This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.

        This exercise is the same as fsm1, but using synchronous reset.

module top_module(clk, reset, in, out);
    input clk;
    input reset;    // Synchronous reset to state B
    input in;
    output out;//  
    reg out;

    // Fill in state name declarations
	
    reg present_state, next_state;
    parameter A = 1'b0;
    parameter B = 1'b1;
    always @(posedge clk) begin
        if (reset) begin  
            // Fill in reset logic
            present_state <= B;
        end
        else begin
            present_state <= next_state;
        end
    end
    always @(*)
        begin
            case(present_state)
                B:begin
                    if(in == 1'b1)
                        next_state <= B;
                    else
                        next_state <= A;
                	end
                A:begin
                    if(in == 1'b1)
                        next_state <= A;
                    else
                        next_state <= B;
                	end
            endcase
        end
          
            always @(*)
                begin
                    if(present_state == B)
                        out <= 1'b1;
                    else
                        out <= 1'b0;
                end

endmodule

题目三

        This is a Moore state machine with two states, two inputs, and one output. Implement this state machine.

        This exercise is the same as fsm2s, but using asynchronous reset.

module top_module(
    input clk,
    input areset,    // Asynchronous reset to OFF
    input j,
    input k,
    output out); //  

    parameter OFF=0, ON=1; 
    reg state, next_state;

    always @(*) begin
        // State transition logic
        case(state)
            OFF:begin
                if(j == 1'b1)
                    next_state <= ON;
                else
                    next_state <= OFF;
            end
            ON:begin
                if(k == 1'b1)
                    next_state <= OFF;
                else
                    next_state <= ON;
            end
        endcase
    end

    always @(posedge clk, posedge areset) begin
        // State flip-flops with asynchronous reset
        if(areset)
            state <= OFF;
        else
            state <= next_state;
    end

    // Output logic
    // assign out = (state == ...);
    assign out = (state == ON);

endmodule

题目四

        This is a Moore state machine with two states, two inputs, and one output. Implement this state machine.

        This exercise is the same as fsm2, but using synchronous reset.

module top_module(
    input clk,
    input reset,    // Synchronous reset to OFF
    input j,
    input k,
    output out); //  

    parameter OFF=0, ON=1; 
    reg state, next_state;

    always @(*) begin
        // State transition logic
        case(state)
            OFF:begin
                if(j == 1'b1)
                    next_state <= ON;
                else
                    next_state <= OFF;
            end
            ON:begin
                if(k == 1'b1)
                    next_state <= OFF;
                else
                    next_state <= ON;
            end
        endcase
                
    end

    always @(posedge clk) begin
        // State flip-flops with synchronous reset
        if(reset)
            state <= OFF;
        else
            state <= next_state;
    end

    // Output logic
    // assign out = (state == ...);
    assign out = (state == ON);
endmodule