FPGA学习笔记（八）------状态机

my_Hello

//状态机  序列检测 Hello
module	my_Hello(clk,rst_n,data,led);

	input clk,rst_n;
	input [7:0] data;		//char

	output reg led;

	localparam    //定义局部参数
		CHACK_H  = 5'b0_0001,
		CHACK_e  = 5'b0_0010,
		CHACK_la = 5'b0_0100,
		CHACK_lb = 5'b0_1000,
		CHACK_o  = 5'b1_0000;
	
	reg	[4:0]	state;
	
	always @ (posedge clk or negedge rst_n)
		if(!rst_n) begin
			state <= CHACK_H;		//复位
			led   <= 1'b0;
		end
		else begin
			case(state)
				CHACK_H: 
					if(data == "H")
						state <= CHACK_e;
					else
						state <= CHACK_H;
				CHACK_e:
					if(data == "e")
						state <= CHACK_la;
					else
						state <= CHACK_H;	
				CHACK_la:
					if(data == "l")
						state <= CHACK_lb;
					else
						state <= CHACK_H;		
				CHACK_lb:
					if(data == "l")
						state <= CHACK_o;
					else
						state <= CHACK_H;		
				CHACK_o:
					if(data == "o")begin
						led <= ~led;
						state <= CHACK_H;	
					end						
					else
						state <= CHACK_H;	
//				CHACK_o:			//写法2
//					begin
//						state <= CHACK_H;
//						if(data == "o")
//							led <= ~led;
//						else
//							led <=  led;
//					end
				default:
					state <= CHACK_H;
			endcase			
		end
endmodule

my_Hello_tb

`timescale 1ns/1ns
`define clock_period 20

module	my_Hello_tb;

	reg	clk,rst_n;
	reg	[7:0]	ASCII;
	
	wire	led;

	my_Hello my_Hello0(
		.clk			(clk),
		.rst_n			(rst_n),
		.data			(ASCII),
		.led			(led)
	);
	
	initial clk = 1;
	always #(`clock_period / 2)	clk = ~clk;
	
	initial begin
		rst_n = 1'b0;
		ASCII = 8'd0;
		#(`clock_period * 200);
		rst_n = 1'b1;
		#(`clock_period * 200+1); //多延时1ns，模拟真实情况
		forever	begin		//永久循环
			ASCII = "Y";
			#(`clock_period );
			ASCII = "u";
			#(`clock_period );			
			ASCII = "X";
			#(`clock_period );			
			ASCII = "i";
			#(`clock_period );
			ASCII = "a";
			#(`clock_period );			
			ASCII = "n";
			#(`clock_period );			
			ASCII = "g";
			#(`clock_period );
	
			ASCII = "H";
			#(`clock_period );			
			ASCII = "E";
			#(`clock_period );			
									
			ASCII = "H";
			#(`clock_period );			
			ASCII = "E";
			#(`clock_period );			
			ASCII = "l";
			#(`clock_period );			
			ASCII = "l";
			#(`clock_period );			
			ASCII = "o";
			#(`clock_period );	
			
			ASCII = "H";
			#(`clock_period );			
			ASCII = "e";
			#(`clock_period );			
			ASCII = "l";
			#(`clock_period );			
			ASCII = "l";
			#(`clock_period );			
			ASCII = "o";
			#(`clock_period );		
		end
	end 
	

endmodule