SystemVerilog dynamic constraint using decorator

systemverilog的constraint也支持decorator(dynamic constraint)

class trans;

  rand bit [9:0] addr;

  constraint cons_addr {  addr inside {[1:100]};   }

  virtual function void rprint();

      this.randomize();

      $display("addr=%0d", addr);

  endfunction

endclass

class decorator extends trans;

  rand trans tr;

  function new(trans tr);   

      this.tr = tr;

  endfunction

  constraint cons_addr { tr.addr == addr; }

endclass

class permit extends decorator; 

  function new(trans tr);

    super.new(tr);

  endfunction

  constraint cons_permit {addr inside {[1:5]}; }

endclass

 

class prohibit extends decorator; 

  function new(trans tr);

    super.new(tr);

  endfunction

  constraint cons_prohibit {addr inside {[5:10]}; }

endclass

module test;

  trans tr; permit per; prohibit pro;

  initial begin

     tr = new();     tr = permit::new(tr); tr = prohibit::new(tr);

     tr.rprint();

endmodule