assertions 使用问答

1.  如何防止在simulation结束仍然还未结束的assertion打印出消息？

VCS supports disabling the SVA unfinished message reporting  at the end of simulation, please do as follows:

1)      Add VCS compile option  “vcs  -assert enable_diag”, which means, enable runtime SVA options

2)      Add VCS runtime option “simv -assert nopostproc” , which means, disable VCS from reporting messages about unfinished assertions at the end of simulation.

 

Then the unfinished message will not be printed on the screen.

2. 如何对assertion进行分类？

DVE supports assertion category, you can use this feature as following:

 

Define assertions with category attribute, for example:

    property hsync;

     @(posedge dClk) (dReset_n) throughout

     $rose(dHsync)|-> ##HPULSE $fell(dHsync);

    endproperty

 

   (* category=1 *) HsyncWidth: assert property ( hsync);

 

    property vsync;

     @(posedge dClk) (dReset_n) throughout

     $rose(dVsync)|-> ##VPULSE $fell(dVsync);

    endproperty

 

     (* category=2 *)  VsyncWidth: assert property ( vsync);

3. cover group 在类中可以有多个instance吗？ cover group 可以带参数吗？

VCS supports coverage groups with arguments, for example:

 

class Scoreboard extends vmm_xactor;

 

covergroup sb_arg_cov (int low, int high);

   covp_blue:coverpoint obj.blu {

     bins covb_blue0 ={[low:high]};

     bins covb_blue1 ={[low+100:high+100]};

 

  }

endgroup:sb_arg_cov

 

 

  function new(string instance = "class",

           Configure cfg,      

           virtual VideoInf.mddisp videoinf);

super.new("Scoreboard", instance);

sb_arg_cov =new(20,30);

endfunction

 

endclass

 

As for the multiple instances of a coverage group that are embedded in the same class, IEE1800 does NOT allow this:

 

18.3 Using covergroup in classes

By embedding a coverage group within a class definition, the covergroup provides a simple way to cover

a subset of the class properties. This integration of coverage with classes provides an intuitive and expressive

mechanism for defining the coverage model associated with a class. For example:

In class xyz, defined below, members m_x and m_y are covered using an embedded covergroup:

class xyz;

bit [3:0] m_x;

int m_y;

bit m_z;

covergroup cov1 @m_z; // embedded covergroup

coverpoint m_x;

coverpoint m_y;

endgroup

function new(); cov1 = new; endfunction

endclass

In this example, data members m_x and m_y of class xyz are sampled on every change of data member m_z.

When a covergroup is defined within a class and no explicit variables of that covergroup are declared in

the class, then a variable with the same name as the coverage group is implicitly declared, e.g, in the above

example, a variable cov1 (of the embedded coverage group) is implicitly declared. Whether the coverage

group variable is implicitly or explicitly declared, each class contains exactly one variable of each embedded

coverage group. Each embedded coverage group thus becomes part of the class, tightly binding the class

properties to the coverage definition. Declaring multiple variables of the same embedded coverage group

shall result in a compiler error.

4. It doesn’t work

Command: vcs +vcs+lic+wait +v2k -Mupdate +notimingcheck +define+PPC_SIM -fsdb -full64 \

-vera -sverilog +verilog2001ext+v +define+ASSERT_ON +define+SVA_VMM_LOG -ntb_opts \

rvm -y /ux/cad3/cad/tools/synopsys/vcs-2010.06/packages/sva +libext+.v +incdir+/ux/cad3/cad/tools/synopsys/vcs-2010.06/packages/sva \

+incdir+../tests/video_out/vo_traffic/hdl +define+MAX_MEM -f ./testbench.f -l ./log/video_out_vo_traffic.log 

why？ 

 the root cause is the option “+verilog2001ext+v”,  which means, once VCS meets “ .v”  files, it use  verilog2001 to compile that file.

The SVA lib has two types of files for a single SVA lib cell, for example:

 

packages/sva/assert_zero_one_hot.sv

packages/sva/assert_zero_one_hot.v

 

You should use “.sv” files. please add following VCS option:

                -y $VCS_HOME/packages/sva +libext+.sv+.v \

 

Then VCS will only compile “.sv” SVA lib files.

5.  How to define Functional coverage in Verilog TB

 

Followingare the brief introductions to implement SV functional coverage in a VerilogTB.

 

Step1. Create an interface file tospy all the DUT internal signals that will be used for functional coverage

 

//******************************************

// usbIntf.sv

//******************************************

 

interface usbIntf (input bitclk);

 

  parameter   SETUP= 1;

  parameter   HOLD  = 1;

 

  logic[7:0] SetupData;

 

  clocking cb_usb @(posedge clk);

    default input #SETUP output #HOLD;

    input  SetupData;

  endclocking

 

endinterface

 

 

Step2. Create your functionalcoverage group in a SV class file:

 

//******************************************

// usbCov.sv

//******************************************

class usbCov;

 

 virtual usbIntf usb_intf;

 

 covergroup cov_usb_setup_payload;

   covp_payload: coverpoint (usb_intf.SetupData) {

   binscovb_data[10]={[1:255]};

   }

   option.per_instance=1;

 endgroup

 

 function new(virtual usbIntf usb_intf);

   this.usb_intf=usb_intf;

   this.cov_usb_setup_payload=new();

 endfunction

 

 virtual task sample_coverage();

   while(1) begin

      repeat(1) @(usb_intf.cb_usb);

      cov_usb_setup_payload.sample();

   end

 endtask

 

endclass

 

 

Step3. Create a test program toinstantiate the coverage model:

 

program automatic cov_test(usbIntfusb_intf);

 

`include"../../sim/cov_model/usbCov.sv"

 //coverage model

 usbCov usb_cov;

 

 

 //sample coverage

 initial begin

   usb_cov=new(usb_intf);

   usb_cov.sample_coverage();

 end

 

 

endprogram

 

Step4. Instantiate the interfaceand test program in your verilog TB Top:

 

 

module tb_top( );

 

//*****************************************************

// functional coverage

//*****************************************************

 

 usbIntf  USBINTF(clk60m);

 assign USBINTF.SetupData=test.pm.RxDataPkt2.SetupData;

 cov_test func_cov(USBINTF);

 

 

//*****************************************************

// DUT-USBPM

//*****************************************************

 

   PmTop pm(

               .rst_n           (rst_n),

               .clk60m          (tmi_clk_30m),

               .clk_gate_uc51   (1'b1),

               .uc_usb_rst      (),

               .rstn_usbpm      (rst_n),

     …

   );

 

 

endmodule

 

Step5. Analyze the coverage report

 

Thecoverage database named “simv.vdb” will be generated automatically when runningsimulations, then you can analyze the report with URG tool.