查找表实现三角函数

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已于 2025-03-27 00:54:47 修改

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分类专栏： BLE 文章标签：前端 verilog fpga fpga开发笔记数字ic

于 2025-03-27 00:54:17 首次发布

本文链接：https://blog.youkuaiyun.com/m0_62785875/article/details/146545151

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首先，我们需要创建一个正弦函数的查找表。假设我们只考虑0到90度的范围，因为正弦函数具有对称性，其他角度的值可以通过简单的数学变换获得。我们将以1度为步长生成这个表。

在Verilog中，我们通常不直接使用浮点数，因此可以将正弦值乘以一个大的常数（这里使用10000）并将结果存储为整数。这样可以在不失太多精度的情况下，使用整数运算。

sine_table是一个数组，存储了从0度到90度的正弦值，每个值都被放大了10000倍。这里只列出了部分值，使用计算工具MATLAB或Python计算出全部的查找表值。

import math

# 生成并打印正弦查找表
for angle in range(91):  # 0到90度
    sine_value = int(math.sin(math.radians(angle)) * 10000)
    print(f"16'd{sine_value},", end=' ')

运行这段Python代码会生成从0度到90度的正弦值，每个值乘以10000并转换为整数。

根据Python生成的结果，以下是Verilog中的查找表:

reg [15:0] sine_table[0:90] = {
    16'd0, 16'd175, 16'd349, 16'd523, 16'd698, 16'd872, 16'd1045, 16'd1218, 16'd1391, 16'd1564,
    16'd1736, 16'd1908, 16'd2079, 16'd2249, 16'd2419, 16'd2588, 16'd2756, 16'd2924, 16'd3090, 16'd3256,
    16'd3420, 16'd3584, 16'd3746, 16'd3907, 16'd4067, 16'd4226, 16'd4384, 16'd4540, 16'd4695, 16'd4848,
    16'd5000, 16'd5150, 16'd5299, 16'd5446, 16'd5592, 16'd5736, 16'd5878, 16'd6018, 16'd6157, 16'd6293,
    16'd6428, 16'd6561, 16'd6691, 16'd6820, 16'd6947, 16'd7071, 16'd7193, 16'd7314, 16'd7431, 16'd7547,
    16'd7660, 16'd7771, 16'd7880, 16'd7987, 16'd8090, 16'd8192, 16'd8290, 16'd8387, 16'd8480, 16'd8572,
    16'd8660, 16'd8746, 16'd8829, 16'd8910, 16'd8988, 16'd9063, 16'd9135, 16'd9205, 16'd9272, 16'd9336,
    16'd9397, 16'd9455, 16'd9511, 16'd9563, 16'd9613, 16'd9659, 16'd9703, 16'd9744, 16'd9783, 16'd9819,
    16'd9853, 16'd9884, 16'd9912, 16'd9937, 16'd9960, 16'd9980, 16'd9997, 17'd10011, 17'd10023, 17'd10031,
    17'd10037, 17'd10040, 17'd10040, 17'd10038, 17'd10033, 17'd10025, 17'd10014, 17'd10000
};

在 Verilog 中定义数组时，如果在模块的内部声明并初始化数组，特别是在使用较大的数组时，可能会遇到一些问题。如果在定义查找表时遇到错误，这可能是因为仿真或综合环境不支持直接在 reg 类型数组的声明中初始化数组。

一种常用的解决方法是在一个 initial 块中初始化数组：

module sine_lookup(
    input [7:0] angle,  // 输入角度，范围0-359
    output reg [15:0] sine_value  // 输出正弦值，放大10000倍
);

// 定义正弦表
reg [15:0] sine_table[0:90];

// 初始化正弦表
initial begin
    sine_table[0] = 16'd0; sine_table[1] = 16'd175; sine_table[2] = 16'd349; sine_table[3] = 16'd523; sine_table[4] = 16'd698;
    sine_table[5] = 16'd872; sine_table[6] = 16'd1045; sine_table[7] = 16'd1218; sine_table[8] = 16'd1391; sine_table[9] = 16'd1564;
    sine_table[10] = 16'd1736; sine_table[11] = 16'd1908; sine_table[12] = 16'd2079; sine_table[13] = 16'd2249; sine_table[14] = 16'd2419;
    sine_table[15] = 16'd2588; sine_table[16] = 16'd2756; sine_table[17] = 16'd2924; sine_table[18] = 16'd3090; sine_table[19] = 16'd3256;
    sine_table[20] = 16'd3420; sine_table[21] = 16'd3584; sine_table[22] = 16'd3746; sine_table[23] = 16'd3907; sine_table[24] = 16'd4067;
    sine_table[25] = 16'd4226; sine_table[26] = 16'd4384; sine_table[27] = 16'd4540; sine_table[28] = 16'd4695; sine_table[29] = 16'd4848;
    sine_table[30] = 16'd5000; sine_table[31] = 16'd5150; sine_table[32] = 16'd5299; sine_table[33] = 16'd5446; sine_table[34] = 16'd5592;
    sine_table[35] = 16'd5736; sine_table[36] = 16'd5878; sine_table[37] = 16'd6018; sine_table[38] = 16'd6157; sine_table[39] = 16'd6293;
    sine_table[40] = 16'd6428; sine_table[41] = 16'd6561; sine_table[42] = 16'd6691; sine_table[43] = 16'd6820; sine_table[44] = 16'd6947;
    sine_table[45] = 16'd7071; sine_table[46] = 16'd7193; sine_table[47] = 16'd7314; sine_table[48] = 16'd7431; sine_table[49] = 16'd7547;
    sine_table[50] = 16'd7660; sine_table[51] = 16'd7771; sine_table[52] = 16'd7880; sine_table[53] = 16'd7987; sine_table[54] = 16'd8090;
    sine_table[55] = 16'd8192; sine_table[56] = 16'd8290; sine_table[57] = 16'd8387; sine_table[58] = 16'd8480; sine_table[59] = 16'd8572;
    sine_table[60] = 16'd8660; sine_table[61] = 16'd8746; sine_table[62] = 16'd8829; sine_table[63] = 16'd8910; sine_table[64] = 16'd8988;
    sine_table[65] = 16'd9063; sine_table[66] = 16'd9135; sine_table[67] = 16'd9205; sine_table[68] = 16'd9272; sine_table[69] = 16'd9336;
    sine_table[70] = 16'd9397; sine_table[71] = 16'd9455; sine_table[72] = 16'd9511; sine_table[73] = 16'd9563; sine_table[74] = 16'd9613;
    sine_table[75] = 16'd9659; sine_table[76] = 16'd9703; sine_table[77] = 16'd9744; sine_table[78] = 16'd9783; sine_table[79] = 16'd9819;
    sine_table[80] = 16'd9853; sine_table[81] = 16'd9884; sine_table[82] = 16'd9912; sine_table[83] = 16'd9937; sine_table[84] = 16'd9960;
    sine_table[85] = 16'd9980; sine_table[86] = 16'd9997; sine_table[87] = 16'd10011; sine_table[88] = 16'd10023; sine_table[89] = 16'd10031;
    sine_table[90] = 17'd10000;
end

// 根据输入角度计算输出正弦值
always @(angle) begin
    if (angle < 90) begin
        sine_value = sine_table[angle];  // 0-90度
    end else if (angle < 180) begin
        sine_value = sine_table[180 - angle];  // 91-180度
    end else if (angle < 270) begin
        sine_value = -sine_table[angle - 180];  // 181-270度
    end else begin
        sine_value = -sine_table[360 - angle];  // 271-360度
    end
end

endmodule

仿真验证结果：

结果符合理论值。