Dedicated to FPGA development for EMC2
Contents
- 1. How to Section
- 2. Hardware
- 3. Software (HDL)
-
- 3.1. http://opencores.org/
- 3.2. http://www.fpga4fun.com/
- 3.3. Aeroflex Gaisler
-
- 4.1. Udp Rx Tx in FPGA
- 4.2. Microcontrollers
-
- 5.1. Protocols
- 5.2. Howto setup rtnet on ubuntu10.04-emc2
- 5.3. Powerlink made Easy
http://en.wikipedia.org/wiki/Field-programmable_gate_array
1. How to Section
See the page http://wiki.linuxcnc.org/cgi-bin/wiki.pl?JTAG_Boundary_Scan_Example_For_A_Mesanet_7i43for information how to get the Xilinx software working.
Simulation: ghdl: http://ghdl.free.fr/ and viewer: GTKWave http://gtkwave.sourceforge.net/
attila.kinali.ch/ghdl.pdf
http://www.dossmatik.de/ghdl/ghdl_unisim.pdf (in german)
VHDL Cookbook: http://www.cs.umbc.edu/portal/help/VHDL/
2. Hardware
http://enterpoint.co.uk/products/spartan-3-development-boards/raggedstone-1/
has two versions: with xc3s400 and xc3s1500 chip.
- small changes to this to get it working with ISE11 and emc2 from ubuntu 8.04
- upload:vhdl-source.tar.gz upload:rs1linuxdriver-0.0.4.tar.gz
- 2011-02-04 this code (vhdl and c) works with ISE12.4 and emc2 from ubuntu 10.04
- testet on rs1-400 and rs1-1500 there is much room for emc spezific logic
-
The http://enterpoint.co.uk/products/modules/pci-io-header-module/
is helpful for programming the board
And if pci slot disappear Raggedstone2 may be a development platform:
http://enterpoint.co.uk/products/spartan-6-development-boards/raggedstone-2/
Digilent Spartan 3E Starter Board
Cheap DP83848-based RMII PHY: http://www.ebay.com/sch/i.html?_nkw=dp83848+kit
3. Software (HDL)
3.1. http://opencores.org/
some for emc interesting projects:- System controller/PCI Target
- Other/PWM/Timer ?/Counter ? (PTC) Core
- Other/quad_decoder
- Communication controller/SPI controller core (and some other spi's)
- Arithmetic core/pid_controler
- Processor/AVR Core (and some other cpu's)
3.2. http://www.fpga4fun.com/
-
http://www.fpga4fun.com/QuadratureDecoder.html
- http://www.fpga4fun.com/EPP.html
- http://www.fpga4fun.com/PCI-Express.html
3.3. Aeroflex Gaisler
- Information about GRETH 10/100 MAC with RMII: http://www.gaisler.com/cms/index.php?option=com_content&task=view&id=199&Itemid=145
- GRLIB VHDL library, GPL license (includes GRETH): http://www.gaisler.com/cms/index.php?option=com_content&task=section&id=13&Itemid=125
4. Non-realtime communication via ethernet
4.1. Udp Rx Tx in FPGA
- http://www.mikrocontroller.net/topic/171526 (look for udpSender.rar and udpReceiver.rar)
-
this is from:
http://itee.uq.edu.au/~peters/xsvboard/index.html look for "VHDL IP Stack"
-
grlib has 100mb mac:
http://www.gaisler.com/cms/index.php?option=com_content&task=section&id=13&Itemid=125
-
for info about MII interface search the internet for "802.3-2008"
-
and find "Part 3: Carrier sense multiple access with Collison Detection (CSMA/CD) Access Method and Physical Layer Specifications"" 802.3-2008_section1.pdf 802.3-2008_section2.pdf
-
upload:udp-tx-jf-2011-02-12.tar.gz
-
this runs on a Digilent Spartan 3E Starter Board (with some startup delay)
- this is a 10Mbit design: sudo ethtool -s eth1 speed 10 duplex full autoneg off
-
http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,792&Prod=S3EBOARD
-
-
ISE12.4: 63 warnings, but it works, occupied slices 6%
- tx_rx upload:udp_tx_rx_vhdl.tar.gz
- sudo arp -i eth1 -s 192.168.2.44 00aaaaaaaaaa
- jjf@nb8:~$ arp
- 192.168.2.44 ether 00:aa:aa:aa:aa:aa CM eth1
- 2011-02-15 today I get an answer from fpga
-
- upload:udp_tx_rx_c.tar.gz this is the small test program
- there is a wrong port in UDPSender.vhd line 347,348!
4.2. Microcontrollers
- The EKC-LMS8962 may be a good starting point for development (Farnell €94)
- 3ph-PWM, 2x quadrature decoder with velocity, A/D(10bit), IEEE 1588 PTP, lwIP and uIP
5. Real Time communication via ethernet
- [Latency of different CPUs]
- [Information about Real-Time Ethernet in Industry Automation]
- [Comparison of latency with networking, Linux/RTAI/Xenomai/VxWorks]
- [Ethernet as a real-time network (last page)]
5.1. Protocols
- RTnet - noncommercial; open; not implemented in any FPGA yet
- Wireshark plugin and raw tcpdump sample data [are available]
- Assuming a network that consists of one computer and one FPGA, most of RTnet can be ignored; when operating full-duplex with only two devices, there is no possibility of a collision.
- Ethernet POWERLINK - commercial; open; work has been done on [an FPGA implementation]
- EtherCAT? - proprietary; synthesizable IP can be licensed from Beckhoff
5.2. Howto setup rtnet on ubuntu10.04-emc2
-
follow (with little changes)
http://www.xenomai.org/index.php/RTnet:Installation_%26_Testing
-
sudo apt-get build-dep emc2
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sudo rm /lib/modules/2.6.32-122-rtai/build/sources
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sudo ln -s /usr/src/linux /lib/modules/2.6.32-122-rtai/build/sources
-
(check that /usr/src/linux is link to /usr/src/linux-2.6.32-122.35-rtai)
-
wget
http://www.rtnet.org/download/rtnet-0.9.12.tar.bz2 and untar to /usr/src/rtnet-0.9.12
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sudo ln -s /usr/src/rtnet-0.9.12 /usr/src/rtnet
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cd /usr/src/rtnet
-
you can select from 3 choices
-
./configure --help and ./configure --enable-8139 --enable-examples --with-rtext=/usr/realtime-2.6.32-122-rtai
-
make menuconfig
-
make gconfig (may require sudo apt-get install glade etc.)
-
./configure --help and ./configure --enable-8139 --enable-examples --with-rtext=/usr/realtime-2.6.32-122-rtai
- make and sudo make install
- sudo mknod /dev/rtnet c 10 240
-
-
my setup is with 2 network cards: lspci
-
unload modules for rtnet-card: sudo rmmod 8139too sudo rmmod 8139cp
-
load rtai-modules
- cd /usr/realtime-2.6.32-122-rtai/modules/
-
sudo insmod ./rtai_hal.ko sudo insmod ./rtai_lxrt.ko sudo insmod ./rtai_sem.ko sudo insmod ./rtdm.ko
-
cd /usr/local/rtnet/
-
edit etc/rtnet.conf for single node with local loopback
- sudo sbin/rtnet start
-
my results
- jjf@emc2-94:/usr/local/rtnet$ sudo sbin/rtping 127.0.0.1
- Real-time PING 127.0.0.1 56(84) bytes of data.
- 64 bytes from 127.0.0.1: icmp_seq=2 time=7.6 us
- 64 bytes from 127.0.0.1: icmp_seq=3 time=8.0 us
- 64 bytes from 127.0.0.1: icmp_seq=4 time=7.5 us
- 64 bytes from 127.0.0.1: icmp_seq=5 time=5.7 us
- 64 bytes from 127.0.0.1: icmp_seq=6 time=5.3 us
- 64 bytes from 127.0.0.1: icmp_seq=7 time=7.3 us
- 64 bytes from 127.0.0.1: icmp_seq=8 time=8.1 us
- 64 bytes from 127.0.0.1: icmp_seq=9 time=5.5 us
-
sudo sbin/rtnet stop
-
edit etc/rtnet.conf for 2 nodes with TDMA_CYCLE=5000 and TDMA_OFFSET=200
-
after sudo sbin/rtnet start on both
- master node: Waiting for all slaves...
-
slave node
- Stage 1: searching for master...
- Stage 2: waiting for other slaves...
- Stage 3: waiting for common setup completion...
-
heavy blinking of switch led's
-
from master node
- jjf@emc2:/usr/local/rtnet$ sudo sbin/rtping 192.168.2.94
- Real-time PING 192.168.2.94 56(84) bytes of data.
- 64 bytes from 192.168.2.94: icmp_seq=1 time=1976.2 us
- 64 bytes from 192.168.2.94: icmp_seq=2 time=2196.3 us
- 64 bytes from 192.168.2.94: icmp_seq=3 time=2196.7 us
-
from slave node
- jjf@emc2-94:/usr/local/rtnet$ sudo sbin/rtping 192.168.2.92
- Real-time PING 192.168.2.92 56(84) bytes of data.
- 64 bytes from 192.168.2.92: icmp_seq=1 time=8956.5 us
- 64 bytes from 192.168.2.92: icmp_seq=2 time=8895.4 us
- 64 bytes from 192.168.2.92: icmp_seq=3 time=8796.1 us
- -
-
with TDMA_CYCLE=2500 and TDMA_OFFSET=200
- ping times master:520µs slave 3300µs
- http://www.rtnet.org/download/Dev04_API-Tutorial.pdf
- http://doc.utwente.nl/53551/kiszka05rtnet.pdf
5.3. Powerlink made Easy
-
http://www.epl-me.org/wiki
-
http://www.epl-me.org/browser/Release here is some hdl code
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