PPC的MCU初始化

MMU初始化重要的有2个，TLB和LAW
通过TLB，把EA(Effective address)转换为RA(Real Address)
通过LAW，把RA送到物理总线上去，即总线地址
下面以MPC8560来举例

-------------------------- 格机格机格机格机格机格机 ------------------------------

Effective Address --> Virtual Address --> Real Address --> Bus Addess
EA 有效地址 VA 虚拟地址 RA 物理地址 总线地址
32 bit 41 bit 32 bit 取决于地址总线位宽

下面是一张图，讲述了TLB把EA转换为RA的过程

第一步：根据 EA有效地址产生 VA虚拟地址。虚拟地址为 41位，构成如下：

bit[0], AS，地址空间域
0 是和中断处理及系统级的代码和数据关联
1 是应用程序的代码和数据

用户模式的程序运行时，一般 MSR[IS,DS]为 1，只允许访问应用程序的代码及数据地址空间。
进入中断时，MSR[IS,DS]自带清 0，因此可以利用系统级的 TLB(TS=0)来访问中断处理相关的代码。 

bit[1-8]，TID，进程标识符
由 PID寄存器提供，多数操作系统都未实现，默认 0

bit[9-40] 即原来的 EA地址 (页表号+页内offset，)

第二步：根据虚拟地址匹配TLB，匹配过程如下：

V域为 1，当前 TLB项有效；
MSR[IS,DS]和 TLB表项的 TS域一致；
TID一致或者 TLB表达 TID为 0，全局共享；
由表项的SIZE域根据公式 n = 32–log2 (page size in bytes)计算虚拟地址中 EPN的值，然后和TLB的 EPN域进行匹配且匹配成功。

第三步，根据TLB生成 RA

TLB匹配成功后，将提取 TLB表的 RPN和 ERPN域，构成 RA物理实际地址的页编号部分，而页内偏移由 EA的低地址部分提供，相关构成如下：

RA = ERPN0:3 || RPN0:n–1 || EAn:31

第四步，匹配LAW，生成总线地址

用RA来检索LAW entry，下面是一个LAW的例子

比如命中了 PCI law entry，就会通过PCI的相关地址转换寄存器生成bus address总线地址，
然后送到PCI总线上

-------------------------- 格机格机格机格机格机格机 ------------------------------

基本原理是用一些静态数组的值来初始化 TLB 和 LAW 的 entry

######################## 文件 /uboot/cpu/mpc8560/start.S #################
221 /*
222 * Invalidate MMU L1/L2
223 *
224 * Note: There is a fixup earlier for Errata CPU4 on
225 * Rev 1 parts that must precede this MMU invalidation.
226 /
227 li r2, 0x001e
228 mtspr MMUCSR0, r2
229 isync
230
231 /
232 * Invalidate all TLB0 entries. 禁用所有TLB0的entry ， 只有4个？
233 /
234 li r3,4
235 li r4,0
236 tlbivax r4,r3
237 /
238 * To avoid REV1 Errata CPU6 issues, make sure
239 * the instruction following tlbivax is not a store.
240 /
241
242 /
243 * After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e.
244 * 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB
245 * region before we can access any CCSR registers such as L2
246 * registers, Local Access Registers,etc. We will also re-allocate
247 * CFG_CCSRBAR_DEFAULT to CFG_CCSRBAR immediately after TLB1 setup.
248 *
249 * Please refer to board-specif directory for TLB1 entry configuration.
250 * (e.g. board//init.S)
251 *
252 /
253 bl tlb1_entry / 注意，tlb1_entry 这个section可以看做一个数组，来描述TLB0和TLB1 /
254 mr r5,r0 / 注意，r0 里存的是第68行的 EA， 此EA里保存的是TLB entry数组的大小值 /
255 li r1,0x0020 / max 16 TLB1 plus some TLB0 entries, 我日，这改Counter寄存器有毛用？/
256 mtctr r1
257 lwzu r4,0(r5) / how many TLB1 entries we actually use 从(r5中存的)EA中load值到r4中，现在r4里面存的是TLB entry 的个数*/
258
259 0: cmpwi r4,0 /* 这就是循环初始化TLB entry了，每初始化一个，r4就减1，r4为0时跳转到第276行*/
260 beq 1f
261 lwzu r0,4(r5) /* r5 在不断的增加4，即EA在不断的增加4，即在遍历TLB entry 数组 /
262 lwzu r1,4(r5)
263 lwzu r2,4(r5)
264 lwzu r3,4(r5)
265 mtspr MAS0,r0 / 用从TLB entry 数组来初始化 TLB /
266 mtspr MAS1,r1
267 mtspr MAS2,r2
268 mtspr MAS3,r3
269 isync
270 msync
271 tlbwe
272 isync
273 addi r4,r4,-1
274 bdnz 0b
275
276 1:
277 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
278 / Special sequence needed to update CCSRBAR itself 即CCSR重定向*/
279 lis r4, CFG_CCSRBAR_DEFAULT@h
280 ori r4, r4, CFG_CCSRBAR_DEFAULT@l
281
282 lis r5, CFG_CCSRBAR@h
283 ori r5, r5, CFG_CCSRBAR@l
284 srwi r6,r5,12
285 stw r6, 0(r4)
286 isync
287
288 lis r5, 0xffff
289 ori r5,r5,0xf000
290 lwz r5, 0(r5)
291 isync
292
293 lis r3, CFG_CCSRBAR@h
294 lwz r5, CFG_CCSRBAR@l(r3)
295 isync
296 #endif
297
298
299 /* set up local access windows, defined at board//init.S /
300 lis r7,CFG_CCSRBAR@h
301 ori r7,r7,CFG_CCSRBAR@l
302
303 bl law_entry / 注意，law_entry 这个section可以看做一个数组，来描述LAW /
304 mr r6,r0 / 注意，r0 里存的是第321行的 EA， 此EA里保存的是LAW entry数组的大小值 /
305
306 li r1,0x0009 / 10 LAWs for MPC8548. The LAWs value in board/init.S must not over the CPU max LAWs. 又是Counter寄存器，初始化它干什么用的？/
307 mtctr r1
308 lwzu r5,0(r6) / how many windows we actually use 从(r6中存的)EA中load值到r5中，现在r5里面存的是TLB entry 的个数*/
309
310 li r2,0x0c28 /* the first pair is reserved for boot-over-rio-or-pci /
311 li r1,0x0c30
312
313 0: cmpwi r5,0 / 循环初始化LAW entry，每初始化一个，r5减1，r5为0时跳转到第325行 /
314 beq 1f
315 lwzu r4,4(r6) / 从(r6中存的)EA中load值, r6也跟着不断增加，即遍历LAW数组 r6 <-- r6+4 r4 <-- *(r6) /
316 lwzu r3,4(r6)
317 stwx r4,r7,r2 / 写LAWBAR寄存器 *(r7+r2) <-- r4 /
318 stwx r3,r7,r1
319 addi r5,r5,-1
320 addi r2,r2,0x0020 / LAWBAR[0-7]寄存器的偏移量是0x0020 r2 <-- r2 + 0x0020 /
321 addi r1,r1,0x0020
322 bdnz 0b
323
324 / Jump out the last 4K page and continue to ‘normal’ start /
325 1: bl 3f
326 b _start
327
328 3: li r0,0
329 mtspr SRR1,r0 / Keep things disabled for now */
330 mflr r1
331 mtspr SRR0,r1
332 rfi

############### 文件 board/pq37pc/pq37pc_8560/init.S ########################

33 /*
34 * TLB0 and TLB1 Entries
35 *
36 * Out of reset, TLB1’s Entry 0 maps the highest 4K for CCSRBAR.
37 * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
38 * these TLB entries are established.
39 *
40 * The TLB entries for DDR are dynamically setup in spd_sdram()
41 * and use TLB1 Entries 8 through 15 as needed according to the
42 * size of DDR memory.
43 *
44 * MAS0: tlbsel, esel, nv
45 * MAS1: valid, iprot, tid, ts, tsize
46 * MAS2: epn, sharen, x0, x1, w, i, m, g, e
47 * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
48 /
49
50 #define entry_start
51 mflr r1 ; \ //把LR的值，即bl tlb1_entry 的下一条指令的EA 保存到 r1 中(即第254行的地址)
52 bl 0f ; // 就是直接跳到0处执行代码，起始就是符号entry_end处(即第55行)
53
54 #define entry_end
55 0: mflr r0 ; \ //把LR的值，即bl 0f的下一条指令的EA 存到 r0 中 (即第68行)
56 mtlr r1 ; \ // 把r1的值放到LR中，LR中值是 bl tlb1_entry的下一条指令的EA (即第254行的地址)
57 blr ; // 跳转到LR处，即执行 bl tlb1_entry的下一条指令 (即第254行的地址)
58
59
60 .section .bootpg, “ax”
61 .globl tlb1_entry
62 tlb1_entry:
63 entry_start
64
65 /
66 * Number of TLB0 and TLB1 entries in the following table
67 /
68 .long 21
69
70 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
71 /
72 * TLB0 4K Non-cacheable, guarded
73 * 0xff700000 4K Initial CCSRBAR mapping
74 *
75 * This ends up at a TLB0 Index==0 entry, and must not collide
76 * with other TLB0 Entries.
77 /
78 .long TLB1_MAS0(0, 0, 0)
79 .long TLB1_MAS1(1, 0, 0, 0, 0)
80 .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
81 .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
82 #else
83 #error(“Update the number of table entries in tlb1_entry”)
84 #endif
85
86 /
87 * TLB0 16K Cacheable, non-guarded
88 * 0xd001_0000 16K Temporary Global data for initialization
89 *
90 * Use four 4K TLB0 entries. These entries must be cacheable
91 * as they provide the bootstrap memory before the memory
92 * controler and real memory have been configured.
93 *
94 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
95 * and must not collide with other TLB0 entries.
96 /
97 .long TLB1_MAS0(0, 0, 0)
98 .long TLB1_MAS1(1, 0, 0, 0, 0)
99 .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),0,0,0,0,0,0,0,0)
100 .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),0,0,0,0,0,1,0,1,0,1)
101
102 .long TLB1_MAS0(0, 0, 0)
103 .long TLB1_MAS1(1, 0, 0, 0, 0)
104 .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),0,0,0,0,0,0,0,0)
105 .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),0,0,0,0,0,1,0,1,0,1)
106
107 .long TLB1_MAS0(0, 0, 0)
108 .long TLB1_MAS1(1, 0, 0, 0, 0)
109 .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),0,0,0,0,0,0,0,0)
110 .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),0,0,0,0,0,1,0,1,0,1)
111
112 .long TLB1_MAS0(0, 0, 0)
113 .long TLB1_MAS1(1, 0, 0, 0, 0)
114 .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),0,0,0,0,0,0,0,0)
115 .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),0,0,0,0,0,1,0,1,0,1)
116
117
118 /
119 * TLB 0: 16M Non-cacheable, guarded
120 * 0xfff80000 512k FLASH
121 * Out of reset this entry is only 4K.
122 /
123 .long TLB1_MAS0(1, 0, 0)
124 .long TLB1_MAS1(1, 1, 0, 0, CFG_MAX_FLASH_TSIZE)
125 .long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_FLASH_BASE), 0,0,0,0,1,0,1,0)
126 .long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_FLASH_BASE), 1,1,1,1,1,1,1,1,0,1)
127
128
129
130 /
131 * TLB 1: 256M Non-cacheable, guarded
132 * 0x80000000 256M PCI1 MEM First half
133 /
134 .long TLB1_MAS0(1, 9, 0)
135 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
136 .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
137 .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
138
139 /
140 * TLB 2: 256M Non-cacheable, guarded
141 * 0x90000000 256M PCI1 MEM Second half
142 /
143 .long TLB1_MAS0(1, 6, 0)
144 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
145 .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),0,0,0,0,1,0,1,0)
146 .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),0,0,0,0,0,1,0,1,0,1)
147
148
149 #if 0
150 /
151 * TLB 3: 256M Non-cacheable, guarded
152 * 0xa0000000 256M Rapid IO MEM First half
153 /
154 .long TLB1_MAS0(1, 7, 0)
155 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
156 .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
157 .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
158
159 /
160 * TLB 4: 256M Non-cacheable, guarded
161 * 0xb0000000 256M Rapid IO MEM Second half
162 /
163 .long TLB1_MAS0(1, 8, 0)
164 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
165 .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),0,0,0,0,1,0,1,0)
166 .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),0,0,0,0,0,1,0,1,0,1)
167
168 #endif
169
170 /
171 * in my design, Rapid IO not use, just use it’s marco for other interface
172 * TLB 3:
173 * 0xa0000000 256M Rapid IO MEM Second half
174 /
175 .long TLB1_MAS0(1, 15, 0)
176 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
177 .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE ),0,0,0,0,1,0,1,0)
178 .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE ),0,0,0,0,0,1,0,1,0,1)
179
180 /
181 * TLB 4: 64M Non-cacheable, guarded
182 * 0xe000_0000 1M CCSRBAR
183 * 0xe200_0000 16M PCI1 IO
184 /
185 .long TLB1_MAS0(1, 1, 0)
186 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
187 .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
188 .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
189
190 /
191 * TLB 5: 16K Non-cacheable, guarded
192 * 0xf8000000 16K registers
193 /
194 .long TLB1_MAS0(1, 10, 0)
195 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K) /BOOKE_PAGESZ_16K for LED_BASE/
196 .long TLB1_MAS2(E500_TLB_EPN(CFG_LED_BASE), 0,0,0,0,1,0,1,0)
197 .long TLB1_MAS3(E500_TLB_RPN(CFG_LED_BASE), 0,0,0,0,0,1,0,1,0,1)
198
199
200 /
201 * TLB 6,7: 128M Non-cacheable, guarded
202 * 0xf0000000 128M registers
203 /
204 .long TLB1_MAS0(1, 11, 0)
205 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
206 .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
207 .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
208
209 .long TLB1_MAS0(1, 12, 0)
210 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
211 .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE + 0x04000000), 0,0,0,0,1,0,1,0)
212 .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE + 0x04000000), 0,0,0,0,0,1,0,1,0,1)
213
214
215
216 /
217 * TLB 8,9,10,11: for 1G DDR
218 * TLB 8 0x00000000 256M DDR System memory
219 * TLB 9 0x10000000 256M DDR System memory
220 * TLB 10 0x20000000 256M DDR System memory
221 * TLB 11 0x30000000 256M DDR System memory
222 * Without SPD EEPROM configured DDR, this must be setup manually.
223 * Make sure the TLB count at the top of this table is correct.
224 * Likely it needs to be increased by two for these entries.
225 /
226 .long TLB1_MAS0(1, 2, 0)
227 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
228 .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
229 .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
230
231 .long TLB1_MAS0(1, 3, 0)
232 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
233 .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x10000000),0,0,0,0,0,0,0,0)
234 .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x10000000),0,0,0,0,0,1,0,1,0,1)
235
236 .long TLB1_MAS0(1, 4, 0)
237 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
238 .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x20000000),0,0,0,0,0,0,0,0)
239 .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x20000000),0,0,0,0,0,1,0,1,0,1)
240
241 .long TLB1_MAS0(1, 5, 0)
242 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
243 .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x30000000),0,0,0,0,0,0,0,0)
244 .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x30000000),0,0,0,0,0,1,0,1,0,1)
245
246 //follow is added by zhangsy
247 /
248 * TLB 12,13,14,15: for 1G DDR
249 * TLB 12 0x40000000 256M DDR System memory
250 * TLB 13 0x50000000 256M DDR System memory
251 * TLB 14 0x60000000 256M DDR System memory
252 * TLB 15 0x70000000 256M DDR System memory
253 /
254
255 .long TLB1_MAS0(1, 7, 0)
256 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
257 .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x40000000), 0,0,0,0,0,0,0,0)
258 .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x40000000), 0,0,0,0,0,1,0,1,0,1)
259
260 .long TLB1_MAS0(1, 8, 0)
261 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
262 .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x50000000),0,0,0,0,0,0,0,0)
263 .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x50000000),0,0,0,0,0,1,0,1,0,1)
264
265 .long TLB1_MAS0(1, 13, 0)
266 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
267 .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x60000000), 0,0,0,0,0,0,0,0)
268 .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x60000000), 0,0,0,0,0,1,0,1,0,1)
269
270 .long TLB1_MAS0(1, 14, 0)
271 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
272 .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x70000000),0,0,0,0,0,0,0,0)
273 .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x70000000),0,0,0,0,0,1,0,1,0,1)
274
275
276 entry_end
277
278 /
279 * LAW(Local Access Window) configuration:
280 *
281 * 0x0000_0000 0x7fff_ffff DDR 2G
282 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
283 * 0xc000_0000 0xdfff_ffff RapidIO 512M
284 * 0xe000_0000 0xe000_ffff CCSR 1M
285 * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
286 * 0xf000_0000 0xf3ff_ffff SDRAM 64M
287 * 0xf800_0000 0xf800_7fff DEBUG LED and board ID 16K
288 * 0xff80_0000 0xffbf_ffff FLASH (2nd bank) 4M
289 * 0xffc0_0000 0xffff_ffff FLASH (boot bank) 4M
290 *
291 * Notes:
292 * CCSRBAR and L2-as-SRAM don’t need a configured Local Access Window.
293 * If flash is 8M at default position (last 8M), no LAW needed.
294 /
295
296 #define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
297 #define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_2G))
298
299 /
300 * Rapid IO at 0xc000_0000 for 512 M
301 /
302 #define LAWBAR3 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
303 #define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
304
305
306
307 / LBC window - maps 256M 0xf0000000 -> 0xffffffff */
308 #define LAWBAR4 ((CFG_LBC_BASE_1>>12) & 0xfffff)
309 #define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI | (LAWAR_SIZE & LAWAR_SIZE_512M))
310
311
312
313 #define LAWBAR5 ((CFG_LBC_BASE_3>>12) & 0xfffff)
314 #define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
315
316
317 .section .bootpg, “ax”
318 .globl law_entry
319 law_entry:
320 entry_start
321 .long 0x04
322 .long LAWBAR0,LAWAR0
323 .long LAWBAR3,LAWAR3
324 .long LAWBAR4,LAWAR4
325 .long LAWBAR5,LAWAR5
326 entry_end