基于xilinx ego1开发板的基础运算计算器

原创于 2024-12-08 17:38:29 发布 · 693 阅读

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#fpga开发

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最近学校数电课程要弄大作业，作者作为一个FPGA的纯新手，只得选择这个看起来最好欺负的选题。但是仍然有很多地方有缺陷，不过好消息是看着像大学生写的，通俗易懂，全篇无需注释你就能看懂，话不多说，上代码。





module calcultor(
    input clk,
    input wire reset,            
    input wire btn_add,           
    input wire btn_sub,           
    input wire btn_mul,           
    input wire btn_div,           
    input wire btn_eq,            
    input[15:0] sw,
      
    output[7:0] seg,
    output[7:0] seg1,
    output[7:0] an 
    
);
    reg[18:0] divclk_cnt = 0;
    reg [7:0] op1;         
    reg [7:0] op2;         
    reg divclk = 0;
    reg [20:0] result;
    
    reg [7:0]op;
    reg[7:0] seg=0;
    reg[7:0] seg1=0;
    reg[7:0] an=8'b00000001;
    reg[20:0] disp_dat=0;
    reg[20:0] data=0;
    reg[2:0] disp_bit=0;
    parameter maxcnt = 50000;
    
    always@(posedge clk)
    begin
        if(divclk_cnt==maxcnt)
        begin
            divclk=~divclk;
            divclk_cnt=0;
        end
        else
        begin
            divclk_cnt=divclk_cnt+1'b1;
        end
    end
    always@(posedge reset)
    begin
        op1=8'b0;
        op2=8'b0;
        disp_dat=21'b0;
        
    end
        
    always@(posedge divclk) begin
        op1=sw[7:0];
        
       
              
        op2=sw[15:8];
        
        if(btn_add)
        result=op1+op2;
        if(btn_sub)
        result=op1-op2;
        if(btn_mul)
        result=op1*op2;
        if(btn_div)
        result=op1/op2;
        
        
        if(disp_bit >= 7)
            disp_bit=0;
         else
            disp_bit=disp_bit+1'b1;
         case (disp_bit)
            3'b000 :
            begin
                disp_dat=result;
                if(disp_dat>9999)
                    data=(((disp_dat%10000)%1000)%100)%10;
                if(disp_dat>999 && disp_dat<10000)
                    data=((disp_dat%1000)%100)%10;
                if(disp_dat>99 && disp_dat<1000)
                    data=(disp_dat%100)%10;
                if(disp_dat>9 && disp_dat<100)
                    data=disp_dat%10;
                if(disp_dat<10)
                    data=disp_dat;
                    
                an=8'b00000001;
            end
            3'b001 :
            begin
                disp_dat=result;
                if(disp_dat>9999)
                    data=(((disp_dat/10)%1000)%100)%10;
                if(disp_dat>999 && disp_dat<10000)
                     data=((disp_dat/10)%100)%10;
                if(disp_dat>99 && disp_dat<1000)
                     data=(disp_dat/10)%10;
                if(disp_dat>9 && disp_dat<100)
                     data=disp_dat/10;
                if(disp_dat<10)
                     data=0;
                an=8'b00000010;
            end
           3'b010:
            begin
                disp_dat=result;
                if(disp_dat>9999)
                    data=((disp_dat/100)%100)%10;
                if(disp_dat<10000 &&disp_dat>999)
                    data=(disp_dat/100)%10;
                if(disp_dat<1000 && disp_dat>99)
                    data=disp_dat/100;
                 if(disp_dat<100)
                    data=0;
                    an=8'b00000100;
             end
             3'b011 :
            begin
                disp_dat=result;
                if(disp_dat>9999)
                    data=(disp_dat/1000)%10;
                if(disp_dat>999 && disp_dat<10000)
                    data=disp_dat/1000;
                 if(disp_dat<1000)
                    data=0;
                an=8'b00001000;
            end
            3'b100 :
            begin
                disp_dat=result;
                if(disp_dat>9999)
                    data=disp_dat/10000;
                else 
                    data=0;
                an=8'b00010000;
            end
            3'b101 :
            begin
                data=0;
                an=8'b00100000;
            end
            3'b110 :
            begin
                data=0;
                an=8'b01000000;
            end
            3'b111 :
            begin
                data=0;
                an=8'b10000000;
            end
        endcase
    end
    
    always@(disp_dat)
    begin
        if(an > 8'b00001000) begin
            case (data)
            //显示0-F
            4'h0 : seg = 8'hfc;
            4'h1 : seg = 8'h60;
            4'h2 : seg = 8'hda;
            4'h3 : seg = 8'hf2;
            4'h4 : seg = 8'h66;
            4'h5 : seg = 8'hb6;
            4'h6 : seg = 8'hbe;
            4'h7 : seg = 8'he0;
            4'h8 : seg = 8'hfe;
            4'h9 : seg = 8'hf6;
           
            endcase
        end
        else begin
            case (data)
            //显示0-F
            4'h0 : seg1 = 8'hfc;
            4'h1 : seg1 = 8'h60;
            4'h2 : seg1 = 8'hda;
            4'h3 : seg1 = 8'hf2;
            4'h4 : seg1 = 8'h66;
            4'h5 : seg1 = 8'hb6;
            4'h6 : seg1 = 8'hbe;
            4'h7 : seg1 = 8'he0;
            4'h8 : seg1 = 8'hfe;
            4'h9 : seg1 = 8'hf6;
            endcase
        end
    end
endmodule


约束条件


## clk
set_property PACKAGE_PIN P17 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
##reset
set_property PACKAGE_PIN P15 [get_ports reset]
set_property IOSTANDARD LVCMOS33 [get_ports reset]
##button
set_property PACKAGE_PIN V1 [get_ports btn_add]
set_property IOSTANDARD LVCMOS33 [get_ports btn_add]
set_property PACKAGE_PIN U4 [get_ports btn_sub]
set_property IOSTANDARD LVCMOS33 [get_ports btn_sub]
set_property PACKAGE_PIN R11 [get_ports btn_mul]
set_property IOSTANDARD LVCMOS33 [get_ports btn_mul]
set_property PACKAGE_PIN R17 [get_ports btn_div]
set_property IOSTANDARD LVCMOS33 [get_ports btn_div]
set_property PACKAGE_PIN R15 [get_ports btn_eq]
set_property IOSTANDARD LVCMOS33 [get_ports btn_eq]
## switch
set_property PACKAGE_PIN N4 [get_ports {sw[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
set_property PACKAGE_PIN R1 [get_ports {sw[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
set_property PACKAGE_PIN R2 [get_ports {sw[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
set_property PACKAGE_PIN M4 [get_ports {sw[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
set_property PACKAGE_PIN P3 [get_ports {sw[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
set_property PACKAGE_PIN P2 [get_ports {sw[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
set_property PACKAGE_PIN P5 [get_ports {sw[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
set_property PACKAGE_PIN P4 [get_ports {sw[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
set_property PACKAGE_PIN T5 [get_ports {sw[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
set_property PACKAGE_PIN V4 [get_ports {sw[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
set_property PACKAGE_PIN R3 [get_ports {sw[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
set_property PACKAGE_PIN V2 [get_ports {sw[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
set_property PACKAGE_PIN V5 [get_ports {sw[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
set_property PACKAGE_PIN U3 [get_ports {sw[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
set_property PACKAGE_PIN U2 [get_ports {sw[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]





##smg位码
set_property PACKAGE_PIN G2 [get_ports an[7]]
set_property IOSTANDARD LVCMOS33 [get_ports an[7]]
set_property PACKAGE_PIN C2 [get_ports an[6]]
set_property IOSTANDARD LVCMOS33 [get_ports an[6]]
set_property PACKAGE_PIN C1 [get_ports an[5]]
set_property IOSTANDARD LVCMOS33 [get_ports an[5]]
set_property PACKAGE_PIN H1 [get_ports an[4]]
set_property IOSTANDARD LVCMOS33 [get_ports an[4]]
set_property PACKAGE_PIN G1 [get_ports an[3]]
set_property IOSTANDARD LVCMOS33 [get_ports an[3]]
set_property PACKAGE_PIN F1 [get_ports an[2]]
set_property IOSTANDARD LVCMOS33 [get_ports an[2]]
set_property PACKAGE_PIN E1 [get_ports an[1]]
set_property IOSTANDARD LVCMOS33 [get_ports an[1]]
set_property PACKAGE_PIN G6 [get_ports an[0]]
set_property IOSTANDARD LVCMOS33 [get_ports an[0]]

## 段码
set_property PACKAGE_PIN B4 [get_ports {seg[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[7]}]
set_property PACKAGE_PIN A4 [get_ports {seg[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
set_property PACKAGE_PIN A3 [get_ports {seg[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
set_property PACKAGE_PIN B1 [get_ports {seg[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
set_property PACKAGE_PIN A1 [get_ports {seg[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
set_property PACKAGE_PIN B3 [get_ports {seg[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
set_property PACKAGE_PIN B2 [get_ports {seg[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
set_property PACKAGE_PIN D5 [get_ports {seg[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]

# 段码2
set_property PACKAGE_PIN D4 [get_ports {seg1[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg1[7]}]
set_property PACKAGE_PIN E3 [get_ports {seg1[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg1[6]}]
set_property PACKAGE_PIN D3 [get_ports {seg1[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg1[5]}]
set_property PACKAGE_PIN F4 [get_ports {seg1[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg1[4]}]
set_property PACKAGE_PIN F3 [get_ports {seg1[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg1[3]}]
set_property PACKAGE_PIN E2 [get_ports {seg1[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg1[2]}]
set_property PACKAGE_PIN D2 [get_ports {seg1[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg1[1]}]
set_property PACKAGE_PIN H2 [get_ports {seg1[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg1[0]}]

部分代码也是从csdn里找的，附带链接https://blog.youkuaiyun.com/unique_ZRF/article/details/127112988

这个代码部分处理的完全是新人水平，目前也只能实现8位的加减乘除运算，希望能帮助到你！

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