HDL bits 做题日常 18/11

1.add2

module top_module (
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);//
    wire [15:0]wsum;
    wire [15:0]wsum2;
    wire w17,w18;
    add16 instance1(.a(a[15:0]), .b(b[15:0]), .cin(0), .cout(w17), .sum(wsum));
                    add16 instance2(.a(a[31:16]), .b(b[31:16]), .cin(w17), .cout(w18), .sum(wsum2));
    assign sum={wsum2,wsum};
 endmodule
module add1 ( input a, input b, input cin, output sum, output cout );
    assign sum=(a^b)^cin;
    assign cout=(a&b)|((a^b)&cin);
// Full adder module here

endmodule

2.carry-select adder

module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire w1;
    wire [15:0]wsum1;
    wire [15:0]wsum2;
    wire [15:0]wsum3;
    add16 instance1(.a(a[15:0]), .b(b[15:0]), .cin(0), .cout(w1), .sum(wsum1));
    add16 instance2(.a(a[31:16]), .b(b[31:16]), .cin(0), .cout(), .sum(wsum2));
    add16 instance3(.a(a[31:16]), .b(b[31:16]), .cin(1), .cout(), .sum(wsum3));
    always@(w1 or wsum2 or wsum3)
        case(w1)
            1'b0: sum<={wsum2,wsum1};
            1'b1: sum<={wsum3,wsum1};
        endcase
endmodule

3.adder-subtractor

module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] sum
);
    wire w1;
    wire [31:0]w2;
    wire [15:0]wsum1;
    wire [15:0]wsum2;
    assign w2=b^{32{sub}};
    add16 instance1(.a(a[15:0]), .b(w2[15:0]), .cin(sub), .cout(w1), .sum(wsum1));
    add16 instance2(.a(a[31:16]), .b(w2[31:16]), .cin(w1), .cout(), .sum(wsum2));
    assign sum={wsum2,wsum1};
endmodule

4.Alwaysblock1

// synthesis verilog_input_version verilog_2001
module top_module(
    input a, 
    input b,
    output wire out_assign,
    output reg out_alwaysblock
);
    assign out_assign=a&b;
    always@(a or b)
        out_alwaysblock=a&b;

endmodule

5.Alwaysblock2

notes:There are three types of assignments in Verilog:

• Continuous assignments (assign x = y;). Can only be used when not inside a procedure ("always block").
• Procedural blocking assignment: (x = y;). Can only be used inside a procedure.
• Procedural non-blocking assignment: (x <= y;). Can only be used inside a procedure.

In a combinational always block, use blocking assignments. In a clocked always block, use non-blocking assignments.

// synthesis verilog_input_version verilog_2001
module top_module(
    input clk,
    input a,
    input b,
    output wire out_assign,
    output reg out_always_comb,
    output reg out_always_ff   );
    assign out_assign=a^b;
    always@(a or b)
        out_always_comb=a^b;
    always@(posedge clk)
        out_always_ff<=a^b;

endmodule

6.always if

notes:

always @(*) begin
    if (condition) begin
        out = x;
    end
    else begin
        out = y;
    end
end

This is equivalent to using a continuous assignment with a conditional operator:

assign out = (condition) ? x : y;

// synthesis verilog_input_version verilog_2001
module top_module(
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output wire out_assign,
    output reg out_always   ); 
    assign out_assign=(sel_b1&sel_b2)?b:a;
    always@(a or b or sel_b1 or sel_b2) begin
        if (sel_b1&sel_b2) begin
                out_always=b;
        end
            else begin
                out_always=a;
            end
        end

endmodule