HDL bits 做题日常02/11

1. no input and one output, ouutput always 1

我：

module top_module( output one );
    assign one ==1'b1;

endmodule

官网solution:

module top_module( output one );
    
    assign one = 1'b1;
    
endmodule

note：==号和=号的区别？为什么不用写 wire one?

2. no input,one output,output always 0

我：

module top_module(
    output zero
);// Module body starts after semicolon
    assign zero=1'b0;
endmodule

官网：

module top_module ( output zero );
    
    assign zero = 1'b0;
    
endmodule

3.Create a module with one input and one output that behaves like a wire.

我：

module top_module( input in, output out );
assign out=in;
endmodule

官网：

module top_module( input in, output out );
    
    assign out = in;
    // Note that wires are directional, so "assign in = out" is not equivalent.
    
endmodule

4. Create a module with 3 inputs and 4 outputs that behaves like wires that makes these connections:a -> w b -> x b -> y c -> z

我：

module top_module( 
    input a,b,c,
    output w,x,y,z );
    assign w=a;
    assign z=c;
    assign x=b;
    assign y=b; //compile success!
endmodule

官网：

module top_module (
    input a,
    input b,
    input c,
    output w,
    output x,
    output y,
    output z  );
    
    assign w = a;
    assign x = b;
    assign y = b;
    assign z = c;

    // If we're certain about the width of each signal, using 
    // the concatenation operator is equivalent and shorter:
    // assign {w,x,y,z} = {a,b,b,c};

5.Create a module that implements a NOT gate.

我：

module top_module( input in, output out );
      assign out=!in;    //compile success!
endmodule

官网:

module top_module(
    input in,
    output out
);
    
    assign out = ~in;
    
endmodule

note: 取反号和非 有什么不同吗 还是在这里都可以使用

6.Create a module that implements an AND gate

我：

module top_module( 
    input a, 
    input b, 
    output out );
    assign out=a&b; //compile success!
endmodule

官网：没找到官网的solution

7.Create a module that implements a NOR gate. A NOR gate is an OR gate with its output inverted. A NOR function needs two operators when written in Verilog.

我：

module top_module( 
    input a, 
    input b, 
    output out );
    wire c;
    assign c=a|b;
    assign out=!c;  //compile success!
endmodule

note: 按位或| 和逻辑运算或|| 本题都可以，是否有更简便的写法呢?

8.Create a module that implements an XNOR gate.

module top_module( 
    input a, 
    input b, 
    output out );
    assign out=a^~b; //compile success!
endmodule

note:The bitwise-XOR operator is ^. There is no logical-XOR operator.

9.Create two intermediate wires (named anything you want) to connect the AND and OR gates together.

我：

`default_nettype none
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 
    wire e,f,g;
    assign e=a&b;
    assign f=c&d;
    assign g=e|f;
    assign out=g;
    assign out_n=!g; //compile success!
endmodule

官网：

module top_module (
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n );
    
    wire w1, w2;        // Declare two wires (named w1 and w2)
    assign w1 = a&b;    // First AND gate
    assign w2 = c&d;    // Second AND gate
    assign out = w1|w2;    // OR gate: Feeds both 'out' and the NOT gate

    assign out_n = ~out;    // NOT gate
    
endmodule

note：哇哦 不用定义g的

10.The 7458 is a chip with four AND gates and two OR gates.

我：

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    wire wire1,wire2,wire3,wire4;
    assign wire1=p2a&p2b;
    assign wire2=p2c&p2d;
    assign p2y=wire1|wire2;
    assign wire3=p1a&p1c&p1b;
    assign wire4=p1f&p1e&p1d;
    assign p1y=wire3|wire4; //compile success!

endmodule