HDL bits---circuits---shift registers-优快云博客

这篇文章描述了一系列Verilog模块，包括数据移位器、循环旋转器、有限状态机和多路复用分频器，展示了如何使用同步时钟和控制信号实现数据处理和逻辑功能。

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1.Shift4

module top_module(
    input clk,
    input areset,  // async active-high reset to zero
    input load,
    input ena,
    input [3:0] data,
    output reg [3:0] q); 
    always@(posedge clk or posedge areset) begin
        if(areset)
            q<=0;
        else if(load==1) begin
            q<=data;
        end
        else if(ena) begin
                q[0]<=q[1];
            q[1]<=q[2];
            q[2]<=q[3];
            q[3]<=0;
        end
            else
                q<=q;
      
    end
endmodule

2.Rotate100

module top_module(
    input clk,
    input load,
    input [1:0] ena,
    input [99:0] data,
    output reg [99:0] q); 
    
    always@(posedge clk) begin
        if(load)
            q<=data;
        else if(ena==2'b10) begin
            for(int i=1;i<100;i=i+1)
                q[i]<=q[i-1];
                q[0]<=q[99];
        end
        else if(ena==2'b01) begin
            for(int m=98;m>-1;m=m-1)
                q[m]<=q[m+1];
                q[99]<=q[0];
        end
        else
            q<=q;
                
          
        
    end
                
endmodule

module top_module(
	input clk,
	input load,
	input [1:0] ena,
	input [99:0] data,
	output reg [99:0] q);
	
	// This rotator has 4 modes:
	//   load
	//   rotate left
	//   rotate right
	//   do nothing
	// I used vector part-select and concatenation to express a rotation.
	// Edge-sensitive always block: Use non-blocking assignments.
	always @(posedge clk) begin
		if (load)		// Load
			q <= data;
		else if (ena == 2'h1)	// Rotate right
			q <= {q[0], q[99:1]};
		else if (ena == 2'h2)	// Rotate left
			q <= {q[98:0], q[99]};
	end
endmodule

3.Shift18

module top_module(
    input clk,
    input load,
    input ena,
    input [1:0] amount,
    input [63:0] data,
    output reg [63:0] q); 
    always@(posedge clk) begin
        if(load)
            q<=data;
        else if(ena) begin
            case(amount)
                2'b00:q<={q[62:0],1'b0};
                2'b01:q<={q[55:0],{8{1'b0}}};
                2'b10:q<={q[63],q[63:1]};
                2'b11:q<={{8{q[63]}},q[63:8]};
                                    
                    
                    endcase
                    end
                    end
                    
endmodule

4.Lfsr5

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 5'h1
    output [4:0] q
); 
    
    
    always@(posedge clk) begin
        
        if(reset)
            q<=5'b00001;
        else 
        
            q<={q[0],q[4],q[3]^q[0],q[2],q[1]};
        
    end
    
endmodule

q[4]<=q[0];
        q[3]<=q[4];
        q[2]<=q[3]^q[0];
        q[1]<=q[2];
        q[0]<=q[1];

为什么如上图这样写不行呢

5.Mt2015 lfsr

module top_module (
	input [2:0] SW,      // R
	input [1:0] KEY,     // L and clk
	output [2:0] LEDR);  // Q
    reg clk;
    assign clk=KEY[0];
    always@(posedge clk) begin
        if(KEY[1])
            LEDR<={SW[2],SW[1],SW[0]};
        else
            LEDR<={LEDR[2]^LEDR[1],LEDR[0],LEDR[2]};
    end

endmodule

6.Lfsr32

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 32'h1
    output [31:0] q
); 
    always@(posedge clk) begin
        if(reset)
            q<=32'h1;
        else
            q<={q[0],q[31:23],q[0]^q[22],q[21:3],q[0]^q[2],q[0]^q[1]};
    end
endmodule

7.Exams/m2014 q4k

module top_module (
    input clk,
    input resetn,   // synchronous reset
    input in,
    output out);
    reg q1,q2,q3;
   
    always@(posedge clk) begin
        if(!resetn)
        {q1,q2,q3,out}<=4'b0;   
        
        else begin
        q1<=in;
        q2<=q1;
        q3<=q2;
        out<=q3;
    end
    end
endmodule

这题我真是操了

8.Exams/2014 q4b

module top_module (
    input [3:0] SW,
    input [3:0] KEY,
    output [3:0] LEDR
); //
    MUXDFF instance1(KEY[3],KEY[1],SW[3],KEY[2],KEY[0],LEDR[3]);
    MUXDFF instance2(LEDR[3],KEY[1],SW[2],KEY[2],KEY[0],LEDR[2]);
    MUXDFF instance3(LEDR[2],KEY[1],SW[1],KEY[2],KEY[0],LEDR[1]);
    MUXDFF instance4(LEDR[1],KEY[1],SW[0],KEY[2],KEY[0],LEDR[0]);
endmodule

module MUXDFF (input
              w,e,r,l,clk,
              output q);
    wire w1,d;
    always@(posedge clk) begin
        q<=d;
    end
    assign w1=e?w:q;
    assign d=l?r:w1;

endmodule

9.Exams/ece241 2013 q12

module top_module (
    input clk,
    input enable,
    input S,
    input A, B, C,
    output Z ); 
    
    reg [7:0] q;
    reg [2:0] ABC;
    assign ABC={A,B,C};
    always@(posedge clk) begin
        if(enable) 
           
            q<={q[6],q[5],q[4],q[3],q[2],q[1],q[0],S};
        
            
        else
            q<=q;
    end
    always@(*) begin
    case(ABC)
            3'b000:Z<=q[0];
            3'b001:Z<=q[1];
            3'b010:Z<=q[2];
            3'b011:Z<=q[3];
            3'b100:Z<=q[4];
            3'b101:Z<=q[5];
            3'b110:Z<=q[6];
            3'b111:Z<=q[7];
     endcase   
    end
       
   
     
endmodule