HDL bits 做题日常 13/11

1.You are given a module my_dff with two inputs and one output (that implements a D flip-flop). Instantiate three of them, then chain them together to make a shift register of length 3. The clk port needs to be connected to all instances.

我：

module top_module ( input clk, input d, output q );
    wire dff12,dff23;
    my_dff instance1(.clk(clk), .d(d), .q(dff12));
    my_dff instance2(.clk(clk), .d(dff12), .q(dff23));
    my_dff instance3(.clk(clk), .d(dff23), .q(q));

endmodule

note:这题错了很久。

官网：

module top_module (
    input clk,
    input d,
    output q
);

    wire a, b;    // Create two wires. I called them a and b.

    // Create three instances of my_dff, with three different instance names (d1, d2, and d3).
    // Connect ports by position: ( input clk, input d, output q)
    my_dff d1 ( clk, d, a );
    my_dff d2 ( clk, a, b );
    my_dff d3 ( clk, b, q );

endmodule

2.modules and vectors

module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);
    wire [7:0] w1;
    wire [7:0] w2;
    wire [7:0] w3;
    wire [7:0] w4;
    wire [1:0] w5;
    my_dff8 instance1(.clk(clk), .d(d), .q(w1));
    my_dff8 instance2(.clk(clk), .d(w1), .q(w2));
    my_dff8 instance3(.clk(clk), .d(w2), .q(w3));
    always@ (sel or d or w1 or w2 or w3)
        case(sel)
            2'b00:q<=d;
            2'b01:q<=w1;
            2'b10:q<=w2;
            2'b11:q<=w3;
        endcase
        
    
endmodule

刚开始想写一个数据选择器的模块，然后再实例化，所以用了好久。。。。

3.module-adder1

module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire w1;
    wire [15:0]w2;
    wire w3;
    wire [15:0]w4;
    assign w3=0;
    add16 instance1(.a(a[15:0]), .b(b[15:0]), .cout(w1), .sum(w2), .cin(w3));
    add16 instance2(.a(a[31:16]), .b(b[31:16]), .cin(w1), .sum(w4), .cout());
    assign sum={w4,w2};

endmodule