F28069M的一些记录

已于 2022-08-23 15:28:40 修改
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分类专栏： TI 文章标签： 单片机 stm32 嵌入式硬件
于 2022-08-17 11:30:04 首次发布
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文章目录

详细技术文档

https://www.ti.com.cn/product/cn/TMS320F28069M

1000多页

SYS_CTRL_REGS系统信息

这个结构体包含了很多F28069M的配置数据

在F2806x_GlobalVariableDefs.c，有这么一段代码，好像是直接去数据区读回来变量，然后跟结构体SYS_CTRL_REGS 关联起来，然后声明一个全局的变量SysCtrlRegs

#ifdef __cplusplus
#pragma DATA_SECTION("SysCtrlRegsFile")
#else
#pragma DATA_SECTION(SysCtrlRegs,"SysCtrlRegsFile");
#endif
volatile struct SYS_CTRL_REGS SysCtrlRegs;

一SYS_CTRL_REGS 结构体


struct SYS_CTRL_REGS {
	union	XCLK_REG		XCLK;			// XCLKOUT Control
	union	PLLSTS_REG		PLLSTS;			// PLL Status Register
	union	CLKCTL_REG		CLKCTL;			// Clock Control Register
	Uint16					PLLLOCKPRD;		// PLL Lock Period Register
	union	INTOSC1TRIM_REG	INTOSC1TRIM;	// Internal Oscillator 1 Trim Register
	Uint16					rsvd1;			// Reserved
	union	INTOSC2TRIM_REG	INTOSC2TRIM;	// Internal Oscillator 2 Trim
	Uint16					rsvd2[2];		// Reserved
	union	PCLKCR2_REG		PCLKCR2;		// Peripheral Clock Control Regsiter 2
	Uint16					rsvd3;			// Reserved
	union	LOSPCP_REG		LOSPCP;			// Low-Speed Peripheral Clock Pre-Scaler Register
	union	PCLKCR0_REG		PCLKCR0;		// Peripheral Clock Control Register 0
	union	PCLKCR1_REG		PCLKCR1;		// Peripheral Clock Control Register 1
	union	LPMCR0_REG		LPMCR0;			// Low Power Mode Control Register 0
	Uint16					rsvd4;			// Reserved
	union	PCLKCR3_REG		PCLKCR3;		// Peripheral Clock Control Register 3
	union	PLLCR_REG		PLLCR;			// PLL Control Register
	Uint16					SCSR;			// System Control and Status Register
	Uint16					WDCNTR;			// Watchdog Counter Register
	Uint16					rsvd5;			// Reserved
	Uint16					WDKEY;			// Watchdog Reset Key Register
	Uint16					rsvd6[3];		// Reserved
	Uint16					WDCR;			// Watchdog Control Register
	union	JTAGDEBUG_REG	JTAGDEBUG;		// JTAG Port Debug Register
	Uint16					rsvd7[5];		// Reserved
	union	PLL2CTL_REG		PLL2CTL;		// PLL2 Configuration Register
	Uint16					rsvd8;			// Reserved
	union	PLL2MULT_REG	PLL2MULT;		// PLL2 Multiplier Register
	Uint16					rsvd9;			// Reserved
	union	PLL2STS_REG		PLL2STS;		// PLL2 Lock Status Register
	Uint16					rsvd10;			// Reserved
	Uint16					SYSCLK2CNTR;	// SYSCLK2 Clock Counter Register
	Uint16					rsvd11[3];		// Reserved
	union	EPWMCFG_REG		EPWMCFG;		// EPWM DMA/CLA Configuration Register
	Uint16					rsvd12[5];		// Reserved
};

1.1 union XCLK_REG XCLK;

1.2 union PLLSTS_REG PLLSTS:PLL相关的寄存器

union PLLSTS_REG {
	Uint16 all;
	struct PLLSTS_BITS	bit;
};

8.6.3 PLL-Based Clock Module
The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes
1 ms. The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of the PLL (VCOCLK) is at least 50 MHz.

1.3 union CLKCTL_REG CLKCTL：时钟控制相关的寄存器寄存器

1.3.2.3 Configuring Device Clock Domains (CLKCTL)
The CLKCTL register is used to choose between the available clock sources and also configure device behavior
during clock failure

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union CLKCTL_REG {
	Uint16 all;
	struct CLKCTL_BITS	bit;
};

1.3.1 例子：切换时钟为内部晶振，关闭其他时钟源

// This function switches to Internal Oscillator 1 and turns off all other clock
// sources to minimize power consumption
void IntOsc1Sel (void) {
    EALLOW;
    SysCtrlRegs.CLKCTL.bit.INTOSC1OFF = 0;
    SysCtrlRegs.CLKCTL.bit.OSCCLKSRCSEL=0;  // Clk Src = INTOSC1
    SysCtrlRegs.CLKCTL.bit.XCLKINOFF=1;     // Turn off XCLKIN
    SysCtrlRegs.CLKCTL.bit.XTALOSCOFF=1;    // Turn off XTALOSC
    SysCtrlRegs.CLKCTL.bit.INTOSC2OFF=1;    // Turn off INTOSC2
    EDIS;
}

晶振主要是指晶体振荡器，而晶体振荡器则是指从一块石英晶体上按照一定的方位角切下来的薄片，我们简称为晶片，是时钟电路中最重要的部件。石英晶体谐振器，简称为石英晶体或晶体、晶振;而在封装内部添加IC组成振荡电路的晶体元件称为晶体振荡器

1.4 Uint16 PLLLOCKPRD; // PLL Lock Period Register

1.5 union INTOSC1TRIM_REG INTOSC1TRIM; // Internal Oscillator 1 Trim Register

1.6 Uint16 rsvd1; // Reserved

1.7 union INTOSC2TRIM_REG INTOSC2TRIM; // Internal Oscillator 2 Trim

1.8 Uint16 rsvd2[2]; // Reserved

1.9 union PCLKCR2_REG PCLKCR2; // Peripheral Clock Control Regsiter 2

1.10 Uint16 rsvd3; // Reserved

1.11 union LOSPCP_REG LOSPCP; // Low-Speed Peripheral Clock Pre-Scaler Register

1.12 union PCLKCR0_REG PCLKCR0：外部时钟控制寄存器？

Peripheral Clock Control Register 0:外部时钟控制寄存器？

1.3.1.1 Enabling/Disabling Clocks to the Peripheral Modules (PCLKCR0/1/2/3

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union PCLKCR0_REG {
	Uint16 all;
	struct PCLKCR0_BITS	bit;
};

###1.12.1 例子：设置ADC的外部时钟

   // *IMPORTANT*
   // The Device_cal function, which copies the ADC & oscillator calibration values
   // from TI reserved OTP into the appropriate trim registers, occurs automatically
   // in the Boot ROM. If the boot ROM code is bypassed during the debug process, the
   // following function MUST be called for the ADC and oscillators to function according
   // to specification. The clocks to the ADC MUST be enabled before calling this
   // function.
   // See the device data manual and/or the ADC Reference
   // Manual for more information.

   EALLOW;
   SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // Enable ADC peripheral clock
   (*Device_cal)();
   SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 0; // Return ADC clock to original state
   EDIS;

1.13 union PCLKCR1_REG PCLKCR1：外部时钟控制寄存器

union PCLKCR1_REG {
	Uint16 all;
	struct PCLKCR1_BITS	bit;
};

1.13.1 example:初始化外部时钟


//--------------------------------------------------------------------------
// Example: InitPeripheralClocks:
//---------------------------------------------------------------------------
// This function initializes the clocks to the peripheral modules.
// First the high and low clock prescalers are set
// Second the clocks are enabled to each peripheral.
// To reduce power, leave clocks to unused peripherals disabled
//
// Note: If a peripherals clock is not enabled then you cannot
// read or write to the registers for that peripheral

void InitPeripheralClocks(void)
{
   EALLOW;

// LOSPCP prescale register settings, normally it will be set to default values

// GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3;  // GPIO18 = XCLKOUT
   SysCtrlRegs.LOSPCP.all = 0x0002;

// XCLKOUT to SYSCLKOUT ratio.  By default XCLKOUT = 1/4 SYSCLKOUT
   SysCtrlRegs.XCLK.bit.XCLKOUTDIV=2;

// Peripheral clock enables set for the selected peripherals.
// If you are not using a peripheral leave the clock off
// to save on power.
//
// Note: not all peripherals are available on all F2806x derivates.
// Refer to the datasheet for your particular device.
//
// This function is not written to be an example of efficient code.

   SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1;    // ePWM1
   SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1;    // ePWM2
   SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1;    // ePWM3
   SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1;    // ePWM4
   SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1;    // ePWM5
   SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1;    // ePWM6
   SysCtrlRegs.PCLKCR1.bit.EPWM7ENCLK = 1;    // ePWM7
   SysCtrlRegs.PCLKCR1.bit.EPWM8ENCLK = 1;    // ePWM8

   SysCtrlRegs.PCLKCR0.bit.HRPWMENCLK = 1;    // HRPWM
   SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;     // Enable TBCLK within the ePWM

   SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 1;    // eQEP1
   SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1;    // eQEP2

   SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 1;    // eCAP1
   SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1;    // eCAP2
   SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1;    // eCAP3

   SysCtrlRegs.PCLKCR2.bit.HRCAP1ENCLK = 1;	  // HRCAP1
   SysCtrlRegs.PCLKCR2.bit.HRCAP2ENCLK = 1;	  // HRCAP2
   SysCtrlRegs.PCLKCR2.bit.HRCAP3ENCLK = 1;	  // HRCAP3
   SysCtrlRegs.PCLKCR2.bit.HRCAP4ENCLK = 1;   // HRCAP4

   SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1;      // ADC
   SysCtrlRegs.PCLKCR3.bit.COMP1ENCLK = 1;    // COMP1
   SysCtrlRegs.PCLKCR3.bit.COMP2ENCLK = 1;    // COMP2
   SysCtrlRegs.PCLKCR3.bit.COMP3ENCLK = 1;    // COMP3

   SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1; // CPU Timer 0
   SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 1; // CPU Timer 1
   SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 1; // CPU Timer 2

   SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1;      // DMA

   SysCtrlRegs.PCLKCR3.bit.CLA1ENCLK = 1;     // CLA1

   SysCtrlRegs.PCLKCR3.bit.USB0ENCLK = 1;	  // USB0 
   
   SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 1;     // I2C-A
   SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 1;     // SPI-A
   SysCtrlRegs.PCLKCR0.bit.SPIBENCLK = 1;     // SPI-B
   SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1;     // SCI-A
   SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1;     // SCI-B
   SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 1;   // McBSP-A
   SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=1;      // eCAN-A
   
   SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;     // Enable TBCLK within the ePWM

   EDIS;
}

1.14 union LPMCR0_REG LPMCR0; // Low Power Mode Control Register 0

1.15 Uint16 rsvd4; // Reserved

1.16 union PCLKCR3_REG PCLKCR3; // Peripheral Clock Control Register 3

1.17 union PLLCR_REG PLLCR; // PLL Control Register

1.18 Uint16 SCSR; // System Control and Status Register

1.19 Uint16 WDCNTR; // Watchdog Counter Register

1.20 Uint16 rsvd5; // Reserved

1.21 Uint16 WDKEY; // Watchdog Reset Key Register

1.22 Uint16 rsvd6[3]; // Reserved

1.23 Uint16 WDCR：看门狗寄存器

1.23.1 例子

下面的代码是演示怎么禁用看门狗

void DisableDog(void)
{
    EALLOW;
    SysCtrlRegs.WDCR= 0x0068;
    EDIS;
}

watch dog是什么
看门狗电路的应用，使单片机可以在无人状态下实现连续工作，其工作原理是:看门狗芯片和单片机的一个I/O引脚相连，该I/O引脚通过程序控制它定时地往看门狗的这个引脚上送入高电平（或低电平），这一程序语句是分散地放在单片机其他控制语句中间的，一旦单片机由于干扰造成程序跑飞后而陷入某一程序段 进入死循环状态时，写看门狗引脚的程序便不能被执行，这个时候，看门狗电路就会由于得不到单片机送来的信号，便在它和单片机复位引脚相连的引脚上送出一个复位信号，使单片机发生复位，即程序从程序存储器的起始位置开始执行，这样便实现了单片机的自动复位。

总结就是 喂狗狗不叫，没人喂了狗就要叫CPU复位

1.24 union JTAGDEBUG_REG JTAGDEBUG; // JTAG Port Debug Register

1.25 Uint16 rsvd7[5]; // Reserved

1.26 union PLL2CTL_REG PLL2CTL; // PLL2 Configuration Register

1.27 Uint16 rsvd8; // Reserved

1.28 union PLL2MULT_REG PLL2MULT; // PLL2 Multiplier Register

1.29 Uint16 rsvd9; // Reserved

1.30 union PLL2STS_REG PLL2STS; // PLL2 Lock Status Register

1.31 Uint16 rsvd10; // Reserved

1.32 Uint16 SYSCLK2CNTR; // SYSCLK2 Clock Counter Register

1.33 Uint16 rsvd11[3]; // Reserved

1.34 union EPWMCFG_REG EPWMCFG; // EPWM DMA/CLA Configuration Register

1.35 Uint16 rsvd12[5]; // Reserved

https://blog.youkuaiyun.com/LSG_Down/article/details/81076878

watch dog是什么

看门狗电路的应用，使单片机可以在无人状态下实现连续工作，其工作原理是:看门狗芯片和单片机的一个I/O引脚相连，该I/O引脚通过程序控制它定时地往看门狗的这个引脚上送入高电平（或低电平），这一程序语句是分散地放在单片机其他控制语句中间的，一旦单片机由于干扰造成程序跑飞后而陷入某一程序段 进入死循环状态时，写看门狗引脚的程序便不能被执行，这个时候，看门狗电路就会由于得不到单片机送来的信号，便在它和单片机复位引脚相连的引脚上送出一个复位信号，使单片机发生复位，即程序从程序存储器的起始位置开始执行，这样便实现了单片机的自动复位。

总结就是 喂狗狗不叫，没人喂了狗就要叫CPU复位

看门狗的机理:

主要核心是一个定时器，当定时器时间到时复位

正常运行程序过程中每次在看门狗的定时器时间到之前重启看门狗定时器

TMS320F2833X 看门狗的组成

1.定时器(计数器) WD Counter 。

2.看门狗重启管理器(WD Reset Register)。

3.看门狗时钟发生器。

4.看门狗状态位

# 二 EALLOW和EDIS语句

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原文：DSP的EALLOW和EDIS指令

三 全局中断 global interrupts

3.1 禁用：DINT

#define  DINT   __asm(" setc INTM")

3.2 启用：EINT

#define  EINT   __asm(" clrc INTM")

四 IFR与IER

4.1 IFR:CPU level interrupt flag,CPU级别的中断标志

IFR = 0x0000;//表示禁用中断

4.2 IER：CPU interrupt enable (IER) register

IER = 0x0000;//表示不启用

五 PIE_VECT_TABLE：中断表？


struct PIE_VECT_TABLE {

// Reset is never fetched from this table.
// It will always be fetched from 0x3FFFC0 in
// boot ROM

      PINT     PIE1_RESERVED;
      PINT     PIE2_RESERVED;
      PINT     PIE3_RESERVED;
      PINT     PIE4_RESERVED;
      PINT     PIE5_RESERVED;
      PINT     PIE6_RESERVED;
      PINT     PIE7_RESERVED;
      PINT     PIE8_RESERVED;
      PINT     PIE9_RESERVED;
      PINT     PIE10_RESERVED;
      PINT     PIE11_RESERVED;
      PINT     PIE12_RESERVED;
      PINT     PIE13_RESERVED;

// Non-Peripheral Interrupts:
      PINT     TINT1;     // CPU-Timer1
      PINT     TINT2;     // CPU-Timer2
      PINT     DATALOG;   // Datalogging interrupt
      PINT     RTOSINT;   // RTOS interrupt
      PINT     EMUINT;    // Emulation interrupt
      PINT     NMI;       // Non-maskable interrupt
      PINT     ILLEGAL;   // Illegal operation TRAP
      PINT     USER1;     // User Defined trap 1
      PINT     USER2;     // User Defined trap 2
      PINT     USER3;     // User Defined trap 3
      PINT     USER4;     // User Defined trap 4
      PINT     USER5;     // User Defined trap 5
      PINT     USER6;     // User Defined trap 6
      PINT     USER7;     // User Defined trap 7
      PINT     USER8;     // User Defined trap 8
      PINT     USER9;     // User Defined trap 9
      PINT     USER10;    // User Defined trap 10
      PINT     USER11;    // User Defined trap 11
      PINT     USER12;    // User Defined trap 12

// Group 1 PIE Peripheral Vectors:
      PINT     ADCINT1;   // ADC - if Group 10 ADCINT1 is enabled, this must be rsvd1_1
      PINT     ADCINT2;   // ADC - if Group 10 ADCINT2 is enabled, this must be rsvd1_2
      PINT     rsvd1_3;
      PINT     XINT1;	  // External Interrupt 1
      PINT     XINT2;     // External Interrupt 2
      PINT     ADCINT9;   // ADC 9
      PINT     TINT0;     // Timer 0
      PINT     WAKEINT;   // WD

// Group 2 PIE Peripheral Vectors:
      PINT     EPWM1_TZINT; // EPWM-1
      PINT     EPWM2_TZINT; // EPWM-2
      PINT     EPWM3_TZINT; // EPWM-3
      PINT     EPWM4_TZINT; // EPWM-4
      PINT     EPWM5_TZINT; // EPWM-5
      PINT     EPWM6_TZINT; // EPWM-6
      PINT     EPWM7_TZINT; // EPWM-7
      PINT     EPWM8_TZINT;	// EPWM-8

// Group 3 PIE Peripheral Vectors:
      PINT     EPWM1_INT;  // EPWM-1
      PINT     EPWM2_INT;  // EPWM-2
      PINT     EPWM3_INT;  // EPWM-3
      PINT     EPWM4_INT;  // EPWM-4
      PINT     EPWM5_INT;  // EPWM-5
      PINT     EPWM6_INT;  // EPWM-6
      PINT     EPWM7_INT;  // EPWM-7
      PINT     EPWM8_INT;  // EPWM-8

// Group 4 PIE Peripheral Vectors:
      PINT     ECAP1_INT;  // ECAP-1
      PINT     ECAP2_INT;  // ECAP-2
      PINT     ECAP3_INT;  // ECAP-3
      PINT     rsvd4_4;
      PINT     rsvd4_5;
      PINT     rsvd4_6;
      PINT     HRCAP1_INT; // HRCAP-1
      PINT     HRCAP2_INT; // HRCAP-2

// Group 5 PIE Peripheral Vectors:
      PINT     EQEP1_INT;  // EQEP-1
      PINT     EQEP2_INT;  // EQEP-2
      PINT     rsvd5_3;
      PINT     HRCAP3_INT; // HRCAP-3
      PINT     HRCAP4_INT; // HRCAP-4
      PINT     rsvd5_6;
      PINT     rsvd5_7;
      PINT     USB0_INT;   // USB-0

// Group 6 PIE Peripheral Vectors:
      PINT     SPIRXINTA; // SPI-A
      PINT     SPITXINTA; // SPI-A
      PINT     SPIRXINTB; // SPI-B
      PINT     SPITXINTB; // SPI-B
      PINT     MRINTA;	  // McBSP-A
      PINT     MXINTA;    // McBSP-A
      PINT     rsvd6_7;
      PINT     rsvd6_8;

// Group 7 PIE Peripheral Vectors:
      PINT     DINTCH1;	// DMA CH1
      PINT     DINTCH2;	// DMA CH2
      PINT     DINTCH3;	// DMA CH3
      PINT     DINTCH4;	// DMA CH4
      PINT     DINTCH5;	// DMA CH5
      PINT     DINTCH6;	// DMA CH6
      PINT     rsvd7_7;
      PINT     rsvd7_8;

// Group 8 PIE Peripheral Vectors:
      PINT     I2CINT1A;  // I2C-A
      PINT     I2CINT2A;  // I2C-A
      PINT     rsvd8_3;
      PINT     rsvd8_4;
      PINT     rsvd8_5;
      PINT     rsvd8_6;
      PINT     rsvd8_7;
      PINT     rsvd8_8;

// Group 9 PIE Peripheral Vectors:

      PINT     SCIRXINTA;  // SCI-A
      PINT     SCITXINTA;  // SCI-A
      PINT     SCIRXINTB;  // SCI-B
      PINT     SCITXINTB;  // SCI-B
      PINT     ECAN0INTA;  // eCAN-A
      PINT     ECAN1INTA;  // eCAN-A
      PINT     rsvd9_7;
      PINT     rsvd9_8;

// Group 10 PIE Peripheral Vectors:
      PINT     rsvd10_1; // Can be ADCINT1, but must make ADCINT1 in Group 1 space "reserved".
      PINT     rsvd10_2; // Can be ADCINT2, but must make ADCINT2 in Group 1 space "reserved".
      PINT     ADCINT3;  // ADC
      PINT     ADCINT4;  // ADC
      PINT     ADCINT5;  // ADC
      PINT     ADCINT6;  // ADC
      PINT     ADCINT7;  // ADC
      PINT     ADCINT8;  // ADC

// Group 11 PIE Peripheral Vectors:

      PINT     CLA1_INT1;  // CLA
      PINT     CLA1_INT2;  // CLA
      PINT     CLA1_INT3;  // CLA
      PINT     CLA1_INT4;  // CLA
      PINT     CLA1_INT5;  // CLA
      PINT     CLA1_INT6;  // CLA
      PINT     CLA1_INT7;  // CLA
      PINT     CLA1_INT8;  // CLA

// Group 12 PIE Peripheral Vectors:
      PINT     XINT3;
      PINT     rsvd12_2;
      PINT     rsvd12_3;
      PINT     rsvd12_4;
      PINT     rsvd12_5;
      PINT     rsvd12_6;
      PINT     LVF;        // Latched overflow
      PINT     LUF;        // Latched underflow
};

5.1 example 设置一个中断回调函数

这个代码来自：Timer based blinking LED Example：Example_2806xLEDBlink.c

    //
    // Interrupts that are used in this example are re-mapped to
    // ISR functions found within this file.
    //
    EALLOW;    // This is needed to write to EALLOW protected registers
    PieVectTable.TINT0 = &cpu_timer0_isr;
    EDIS;      // This is needed to disable write to EALLOW protected registers

六 PIE_CTRL_REGS ：中断表相关的寄存器？

struct PIE_CTRL_REGS {
	union	PIECTRL_REG	PIECTRL;	// PIE Control Register
	union	PIEACK_REG	PIEACK;		// PIE Acknowledge Register
	union	PIEIER_REG	PIEIER1;	// PIE INT1 IER Register
	union	PIEIFR_REG	PIEIFR1;	// PIE INT1 IFR Register
	union	PIEIER_REG	PIEIER2;	// PIE INT2 IER Register
	union	PIEIFR_REG	PIEIFR2;	// PIE INT2 IFR Register
	union	PIEIER_REG	PIEIER3;	// PIE INT3 IER Register
	union	PIEIFR_REG	PIEIFR3;	// PIE INT3 IFR Register
	union	PIEIER_REG	PIEIER4;	// PIE INT4 IER Register
	union	PIEIFR_REG	PIEIFR4;	// PIE INT4 IFR Register
	union	PIEIER_REG	PIEIER5;	// PIE INT5 IER Register
	union	PIEIFR_REG	PIEIFR5;	// PIE INT5 IFR Register
	union	PIEIER_REG	PIEIER6;	// PIE INT6 IER Register
	union	PIEIFR_REG	PIEIFR6;	// PIE INT6 IFR Register
	union	PIEIER_REG	PIEIER7;	// PIE INT7 IER Register
	union	PIEIFR_REG	PIEIFR7;	// PIE INT7 IFR Register
	union	PIEIER_REG	PIEIER8;	// PIE INT8 IER Register
	union	PIEIFR_REG	PIEIFR8;	// PIE INT8 IFR Register
	union	PIEIER_REG	PIEIER9;	// PIE INT9 IER Register
	union	PIEIFR_REG	PIEIFR9;	// PIE INT9 IFR Register
	union	PIEIER_REG	PIEIER10;	// PIE INT10 IER Register
	union	PIEIFR_REG	PIEIFR10;	// PIE INT10 IFR Register
	union	PIEIER_REG	PIEIER11;	// PIE INT11 IER Register
	union	PIEIFR_REG	PIEIFR11;	// PIE INT11 IFR Register
	union	PIEIER_REG	PIEIER12;	// PIE INT12 IER Register
	union	PIEIFR_REG	PIEIFR12;	// PIE INT12 IFR Register
};

6.1 example:启用PIE 表

// Enable the PIE Vector Table
	PieCtrlRegs.PIECTRL.bit.ENPIE = 1;

七 CPUTIMER_VARS：CPU定时器相关

// CPU Timer Support Variables:
//
struct CPUTIMER_VARS {
   volatile struct  CPUTIMER_REGS  *RegsAddr;
   Uint32    InterruptCount;
   float   CPUFreqInMHz;
   float   PeriodInUSec;
};

7.1 example cpu定时的初始化

#ifdef __cplusplus
#pragma DATA_SECTION("CpuTimer0RegsFile")
#else
#pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile");
#endif
volatile struct CPUTIMER_REGS CpuTimer0Regs;
//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("CpuTimer1RegsFile")
#else
#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile");
#endif
volatile struct CPUTIMER_REGS CpuTimer1Regs;

//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("CpuTimer2RegsFile")
#else
#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile");
#endif
volatile struct CPUTIMER_REGS CpuTimer2Regs;
 

void InitCpuTimers(void)
{
    // CPU Timer 0
	// Initialize address pointers to respective timer registers:
	CpuTimer0.RegsAddr = &CpuTimer0Regs;//看代码开头
	// Initialize timer period to maximum:
	CpuTimer0Regs.PRD.all  = 0xFFFFFFFF;
	// Initialize pre-scale counter to divide by 1 (SYSCLKOUT):
	CpuTimer0Regs.TPR.all  = 0;
	CpuTimer0Regs.TPRH.all = 0;
	// Make sure timer is stopped:
	CpuTimer0Regs.TCR.bit.TSS = 1;
	// Reload all counter register with period value:
	CpuTimer0Regs.TCR.bit.TRB = 1;
	// Reset interrupt counters:
	//CpuTimer0.InterruptCount = 0;


// Initialize address pointers to respective timer registers:
	CpuTimer1.RegsAddr = &CpuTimer1Regs;
	CpuTimer2.RegsAddr = &CpuTimer2Regs;
	// Initialize timer period to maximum:
	CpuTimer1Regs.PRD.all  = 0xFFFFFFFF;
	CpuTimer2Regs.PRD.all  = 0xFFFFFFFF;
    // Initialize pre-scale counter to divide by 1 (SYSCLKOUT):
	CpuTimer1Regs.TPR.all  = 0;
	CpuTimer1Regs.TPRH.all = 0;
	CpuTimer2Regs.TPR.all  = 0;
	CpuTimer2Regs.TPRH.all = 0;
    // Make sure timers are stopped:
	CpuTimer1Regs.TCR.bit.TSS = 1;
	CpuTimer2Regs.TCR.bit.TSS = 1;
	// Reload all counter register with period value:
	CpuTimer1Regs.TCR.bit.TRB = 1;
	CpuTimer2Regs.TCR.bit.TRB = 1;
	// Reset interrupt counters:
	//CpuTimer1.InterruptCount = 0;
	//CpuTimer2.InterruptCount = 0;

}

7.2 example 设置定时器触发的周期

上面PIE关联一个中断函数到INT0，这个是timer0回调的函数指针。
下面的代码就是设置timer0 500毫秒回调一次

//---------------------------------------------------------------------------
// ConfigCpuTimer:
//---------------------------------------------------------------------------
// This function initializes the selected timer to the period specified
// by the "Freq" and "Period" parameters. The "Freq" is entered as "MHz"
// and the period in "uSeconds". The timer is held in the stopped state
// after configuration.
//
void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period)
{
	Uint32 	PeriodInClocks;

	// Initialize timer period:
	Timer->CPUFreqInMHz = Freq;
	Timer->PeriodInUSec = Period;
	PeriodInClocks = (long) (Freq * Period);
	Timer->RegsAddr->PRD.all = PeriodInClocks - 1; // Counter decrements PRD+1 times each period

	// Set pre-scale counter to divide by 1 (SYSCLKOUT):
	Timer->RegsAddr->TPR.all  = 0;
	Timer->RegsAddr->TPRH.all  = 0;

	// Initialize timer control register:
	Timer->RegsAddr->TCR.bit.TSS = 1;      // 1 = Stop timer, 0 = Start/Restart Timer
	Timer->RegsAddr->TCR.bit.TRB = 1;      // 1 = reload timer
	Timer->RegsAddr->TCR.bit.SOFT = 0;
	Timer->RegsAddr->TCR.bit.FREE = 0;     // Timer Free Run Disabled
	Timer->RegsAddr->TCR.bit.TIE = 1;      // 0 = Disable/ 1 = Enable Timer Interrupt

	// Reset interrupt counter:
	Timer->InterruptCount = 0;

}

八 GPIO_CTRL_REGS:GPIO设置相关寄存器


//----------------------------------------
#ifdef __cplusplus
#pragma DATA_SECTION("GpioCtrlRegsFile")
#else
#pragma DATA_SECTION(GpioCtrlRegs,"GpioCtrlRegsFile");
#endif
volatile struct GPIO_CTRL_REGS GpioCtrlRegs;


struct GPIO_CTRL_REGS {
	union	GPACTRL_REG		GPACTRL;	// GPIO A Control Register (GPIO0 to 31)
	union	GPA1_REG		GPAQSEL1;	// GPIO A Qualifier Select 1 Register (GPIO0 to 15)
	union	GPA2_REG		GPAQSEL2;	// GPIO A Qualifier Select 2 Register (GPIO16 to 31)
	union	GPA1_REG		GPAMUX1;	// GPIO A Mux 1 Register (GPIO0 to 15)
	union	GPA2_REG		GPAMUX2;	// GPIO A Mux 2 Register (GPIO16 to 31)
	union	GPADAT_REG		GPADIR;		// GPIO A Direction Register (GPIO0 to 31) )
	union	GPADAT_REG		GPAPUD;		// GPIO A Pull-Up Disable Register
	union	GPACTRL2_REG	GPACTRL2;	// GPIO A Control Register 2
	Uint16					rsvd1;		// Reserved
	union	GPBCTRL_REG		GPBCTRL;	// GPIO B Control Register (GPIO32 to 63)
	union	GPB1_REG		GPBQSEL1;	// GPIO B Qualifier Select 1 Register (GPIO32 to 47)
	union	GPB2_REG		GPBQSEL2;	// GPIO B Qualifier Select 2 Register (GPIO48 to 63)
	union	GPB1_REG		GPBMUX1;	// GPIO B Mux 1 Register (GPIO32 to 47)
	union	GPB2_REG		GPBMUX2;	// GPIO B Mux 2 Register (GPIO48 to 63)
	union	GPBDAT_REG		GPBDIR;		// GPIO B Direction Register (GPIO32 to 63)
	union	GPBDAT_REG		GPBPUD;		// GPIO B Pull-Up Disable Register
	Uint16					rsvd2[24];	// Reserved
	union	AIO_REG			AIOMUX1;	// Analog IO Mux 1 Register
	Uint16					rsvd3[2];	// Reserved
	union	AIODAT_REG		AIODIR;		// Analog IO Direction Register
	Uint16					rsvd4[4];	// Reserved
};

8.1 example 设置GPIO34为输出pin

GPB1_REG：GPIO32 to 47
GPB2_REG：GPIO48 to 63

    //
    // Configure GPIO34 as a GPIO output pin
    //
    EALLOW;
    GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0;
    GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1;
    EDIS;

九 EQEP_REGS 编码器相关寄存器

在这里插入图片描述

struct EQEP_REGS {
	Uint32				QPOSCNT;	// Position Counter
	Uint32				QPOSINIT;	// Position Counter Init
	Uint32				QPOSMAX;	// Maximum Position Count
	Uint32				QPOSCMP;	// Position Compare
	Uint32				QPOSILAT;	// Index Position Latch
	Uint32				QPOSSLAT;	// Strobe Position Latch
	Uint32				QPOSLAT;	// Position Latch
	Uint32				QUTMR;		// QEP Unit Timer
	Uint32				QUPRD;		// QEP Unit Period
	Uint16				QWDTMR;		// QEP Watchdog Timer
	Uint16				QWDPRD;		// QEP Watchdog Period
	union	QDECCTL_REG	QDECCTL;	// Quadrature Decoder Control
	union	QEPCTL_REG	QEPCTL;		// QEP Control
	union	QCAPCTL_REG	QCAPCTL;	// Qaudrature Capture Control
	union	QPOSCTL_REG	QPOSCTL;	// Position Compare Control
	union	QEINT_REG	QEINT;		// QEP Interrupt Control
	union	QFLG_REG	QFLG;		// QEP Interrupt Flag
	union	QFLG_REG	QCLR;		// QEP Interrupt Clear
	union	QFRC_REG	QFRC;		// QEP Interrupt Force
	union	QEPSTS_REG	QEPSTS;		// QEP Status
	Uint16				QCTMR;		// QEP Capture Timer
	Uint16				QCPRD;		// QEP Capture Period
	Uint16				QCTMRLAT;	// QEP Capture Latch
	Uint16				QCPRDLAT;	// QEP Capture Period Latch
	Uint16				rsvd1;		// Reserved
};
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