Fsm3 Fsm3

最新推荐文章于 2023-08-09 23:05:37 发布

原创最新推荐文章于 2023-08-09 23:05:37 发布 · 389 阅读

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文章详细描述了如何使用Verilog语言设计一个具有一个输入、一个输出和四个状态的Moore型状态机，并包含一个异步重置功能，将状态机重置回初始状态A。两种不同的状态机实现方式被展示，包括状态转移逻辑和输出逻辑的代码。

The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include an asynchronous reset that resets the FSM to state A.

一种写法

module top_module(
    input clk,
    input in,
    input areset,
    output out); //
	
    parameter A = 2'b00,
    		B = 2'b01,
    		C = 2'b11,
    		D = 2'b10;
    reg [1:0] state;
    reg [1:0] next_state;
    
    // State transition logic
    always@ (*) begin
          case(state)
                A:if(in == 1)
                    	next_state <= B;
                		else
                            next_state <= A;
                B:if(in == 0)
                    	next_state <= C;
                		else
                            next_state <= B;
                C:if(in == 1)
                    	next_state <= D;
                		else
                            next_state <= A;
                D:if(in == 1)
                    	next_state <= B;
                		else
                            next_state <= C;
				default:   next_state <= A;  
            endcase
    end
    
    // State flip-flops with asynchronous reset
    always@(posedge clk or posedge areset)
        if(areset)
            state <= A;
    	else 
         state  <= next_state;
           
    // Output logic
	assign out = state == D ? 1'b1 : 1'b0;
endmodule

另一种写法

module top_module(
    input clk,
    input in,
    input areset,
    output out); //
	
    parameter A = 2'b00,
    		B = 2'b01,
    		C = 2'b11,
    		D = 2'b10;
    reg [1:0] state;
    reg [1:0] next_state;
    
    // State transition logic
    always@ (*) begin
          state  <= next_state;
    end
   
    // State flip-flops with asynchronous reset
    always@(posedge clk or posedge areset)
        if(areset)
            next_state <= A;
    	else 
          case(next_state)
                A:if(in == 1)
                    	next_state <= B;
                		else
                            next_state <= A;
                B:if(in == 0)
                    	next_state <= C;
                		else
                            next_state <= B;
                C:if(in == 1)
                    	next_state <= D;
                		else
                            next_state <= A;
                D:if(in == 1)
                    	next_state <= B;
                		else
                            next_state <= C;
				default:   next_state <= A;  
            endcase
           
    // Output logic
	assign out = state == D ? 1'b1 : 1'b0;
endmodule