Exams/ece241 2013 q12

eachanm

于 2023-07-30 22:33:00 发布

阅读量308

点赞数

CC 4.0 BY-SA版权

分类专栏： HDLBits题目文章标签： verilog

本文链接：https://blog.youkuaiyun.com/eachanm/article/details/132012774

HDLBits题目专栏收录该内容

95 篇文章

订阅专栏

设计了一个基于8位移位寄存器的电路，该电路具有写入时移位和读取时随机访问的功能。通过3个输入A、B、C和输出Z，实现3输入逻辑函数，其中Z的值由A、B、C的组合决定，映射到移位寄存器的相应位。在时钟上升沿且使能信号有效时，数据向移位寄存器移位。

摘要生成于 C知道，由 DeepSeek-R1 满血版支持，前往体验 >

In this question, you will design a circuit for an 8x1 memory, where writing to the memory is accomplished by shifting-in bits, and reading is "random access", as in a typical RAM. You will then use the circuit to realize a 3-input logic function.

First, create an 8-bit shift register with 8 D-type flip-flops. Label the flip-flop outputs from Q[0]...Q[7]. The shift register input should be called S, which feeds the input of Q[0] (MSB is shifted in first). The enable input controls whether to shift. Then, extend the circuit to have 3 additional inputs A,B,C and an output Z. The circuit's behaviour should be as follows: when ABC is 000, Z=Q[0], when ABC is 001, Z=Q[1], and so on. Your circuit should contain ONLY the 8-bit shift register, and multiplexers. (Aside: this circuit is called a 3-input look-up-table (LUT)).

module top_module (
    input clk,
    input enable,
    input S,
    input A, B, C,
    output Z ); 

    reg [7:0] Q;
    always@ (posedge clk)
       if(enable)
           Q <= {Q[6:0],S};
        
        
    always@ (*)
            case({A, B, C})
                3'b000: Z <= Q[0];
                3'b001: Z <= Q[1];
                3'b010:Z <= Q[2];
                3'b011:Z <= Q[3];
                3'b100:Z <= Q[4];
                3'b101:Z <= Q[5];
                3'b110:Z <= Q[6];
                3'b111:Z <= Q[7];
                default: Z <= Q[0];
            endcase    
endmodule