首先要理解的是利用D触发器实现2分频的思路:
verilog代码如下:
module div_2 (
input clk_in,
input rst ,
output clk_out
);
reg clk;
always @( posedge clk or negedge rst )
begin
if( !rst )
clk<= 1'h0;
else
clk<=~clk;
end
assign clk_out =clk;endmodule
4分频的设计是基于2分频再2分频实现的代码如下:
module div_2(
input clk_in,
input rst,
//output clk_out_1
output clk_out
);
reg clk ;
wire clk_out_1;
reg clk_2;
// wire clk_m;
always @(posedge clk_in or negedge rst )
if(!rst)
begin
clk<= 1'h0;
clk_2 <= 1'b0;
end
else
begin
clk<= ~clk;
end
assign clk_out_1 = clk;
always @ (posedge clk_out_1)
if(!rst)
begin
clk_2 <= 1'b0;
end
else
begin
clk_2 <= ~clk_2;
end
assign clk_out = clk_2;
endmodule
下面附上仿真图: