/*
* ifado.dtsi
- Sigmastar
*
* Copyright (c) [2019~2020] SigmaStar Technology.
*
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License version 2 for more details.
*
*/
#include <generated/autoconf.h>
#include "../../../include/configs/ifado.h"
#include "../../../drivers/sstar/include/ifado/gpio.h"
/* retain smf for multicore wakening */
/memreserve/ 0x20000000 0x00002000;
/ {
cpus {
#address
-cells = <1>;
#size
-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex
-a7";
clock
-frequency = <1200000000>;
//clocks = <&CLK_cpupll_clk>;
reg = <0x0>;
};
};
aliases {
console = &uart0;
serial0 = &uart0;
};
#ifdef CONFIG_OPTEE
firmware {
optee {
compatible = "linaro,optee
-tz";
method = "smc";
};
};
#endif
soc {
compatible = "simple
-bus";
#address
-cells = <1>;
#size
-cells = <1>;
dma
-ranges = <0x0 CONFIG_SYS_SDRAM_BASE CONFIG_UBOOT_RAM_SIZE>;
ranges;
clks: clocks{
#address
-cells = <1>;
#size
-cells = <1>;
ranges;
};
watchdog: watchdog {
compatible = "sstar,wdt";
reg = <0x1F006000 0x40>;
status = "okay";
};
uart0: uart@1F221000 {
compatible = "sstar,uart";
reg = <0x1F221000 0x100>;
status = "okay";
};
gpio: gpio {
compatible = "sstar,gpio";
status = "okay";
};
adclp: adclp {
compatible = "sstar,adclp";
reg = <0x1F002800 0x200>;
chan
-num = <4>;
ref
-voltage = <1800>;
status = "okay";
};
pwm0: pwm@0x1F003400{
compatible = "sstar,pwm";
reg = <0x1F003400 0x37>;
channel = <0>;
clock
-freq = <12000000>;
status = "okay";
};
pwm1: pwm@0x1F003480 {
compatible = "sstar,pwm";
reg = <0x1F003480 0x37>;
channel = <1>;
clock
-freq = <12000000>;
status = "okay";
};
pwm2: pwm@0x1F003500 {
compatible = "sstar,pwm";
reg = <0x1F003500 0x37>;
channel = <2>;
clock
-freq = <12000000>;
status = "okay";
};
pwm3: pwm@0x1F003580 {
compatible = "sstar,pwm";
reg = <0x1F003580 0x37>;
channel = <3>;
clock
-freq = <12000000>;
status = "okay";
};
pwm4: pwm@0x1F003600 {
compatible = "sstar,pwm";
reg = <0x1F003600 0x37>;
channel = <4>;
clock
-freq = <12000000>;
status = "okay";
};
pwm5: pwm@0x1F003680 {
compatible = "sstar,pwm";
reg = <0x1F003680 0x37>;
channel = <5>;
clock
-freq = <12000000>;
status = "okay";
};
pwm6: pwm@0x1F003700 {
compatible = "sstar,pwm";
reg = <0x1F003700 0x37>;
channel = <6>;
clock
-freq = <12000000>;
status = "okay";
};
pwm7: pwm@0x1F003780 {
compatible = "sstar,pwm";
reg = <0x1F003780 0x37>;
channel = <7>;
clock
-freq = <12000000>;
status = "okay";
};
pwm8: pwm@0x1F003800 {
compatible = "sstar,pwm";
reg = <0x1F003800 0x37>;
channel = <8>;
clock
-freq = <12000000>;
status = "okay";
};
pwm9: pwm@0x1F003880 {
compatible = "sstar,pwm";
reg = <0x1F003880 0x37>;
channel = <9>;
clock
-freq = <12000000>;
status = "okay";
};
pwm10: pwm@0x1F003900 {
compatible = "sstar,pwm";
reg = <0x1F003900 0x37>;
channel = <10>;
clock
-freq = <12000000>;
status = "okay";
};
msb250x_
udc_p0: sstar
-udc-p0@1f284a00 {
compatible = "sstar,msb250x
-udc";
reg = <0x1f284000 0x200>, <0x1f284200 0x200>, <0x1f284600 0x200>, <0x1f284a00 0x200>, <0x1f285200 0x200>;
reg
-names = "upll", "utmi", "usb0", "otg", "extra_utmi_power";
status = "okay";
};
sstar_ehci_p0: sstar
-ehci
-p0@1f284800 {
compatible = "sstar,ehci";
reg = <0x1f284000 0x200>, <0x1f284200 0x200>, <0x1f284400 0x200>, <0x1f284600 0x200>, <0x1f284800 0x200>, <0x1f285200 0x200>;
reg
-names = "upll", "utmi", "bc", "usb0", "ehc", "extra_utmi_power";
status = "okay";
};
sstar_mmc0: sstar_mmc0 {
compatible = "sstar
-mmc";
bus
-width = <4>;
max
-frequency = <48000000>;
cap
-mmc
-highspeed = <1>;
ip
-order = <0>;
pad
-order = <0>;
pwr
-on
-delay = <10>;
pwr
-off
-delay = <50>;
fake
-cdz = <0>;
rev
-cdz = <0>;
pwr
-pad = <PAD_FUART_RTS>;
cdz
-pad = <PAD_PM_SD_CDZ>;
clk
-driving = <1>;
cmd
-driving = <1>;
data
-driving = <1>;
en
-clk
-phase = <0>;
rx
-clk
-phase = <0>;
tx
-clk
-phase = <0>;
status = "okay";
};
sstar_mmc1: sstar_mmc1 {
compatible = "sstar
-mmc";
bus
-width = <8>;
max
-frequency = <48000000>;
cap
-mmc
-highspeed = <1>;
ip
-order = <1>;
pad
-order = <0>;
pwr
-on
-delay = <10>;
pwr
-off
-delay = <50>;
fake
-cdz = <0>;
rev
-cdz = <0>;
pwr
-pad = <PAD_PM_GPIO9>;
cdz
-pad = <PAD_SD1_IO6>;
clk
-driving = <1>;
cmd
-driving = <1>;
data
-driving = <1>;
en
-clk
-phase = <0>;
rx
-clk
-phase = <0>;
tx
-clk
-phase = <0>;
non
-removable = <1>;
status = "okay";
};
usbpll: usb
-pll {
compatible = "sstar,generic
-usbpll";
reg = <0x1f283c00 0x200>;
#clock
-cells = <0>;
status = "okay";
};
u3phy_utmi: utmi@1f286e00 {
compatible = "sstar,generic
-utmi";
reg = <0x1f286e00 0x200>;
clocks = <&usbpll>;
sstar,tx
-swing
-and
-de
-emphasis = <0x3f>, <0x1a>, <0x07>;
sstar,only
-for
-dwc3;
#phy
-cells = <0>;
status = "okay";
};
u3phy_pipe: pipe@1f2a5200 {
compatible = "sstar,generic
-pipe";
reg = <0x1f2a5200 0x800>;
//clocks = <&CLK_ssusb_phy_108>, <&CLK_ssusb_phy_432>;
sstar,synthesiszer
-clk = <0x001ba5e3>;
sstar,tx
-swing
-and
-de
-emphasis = <0x3f>, <0x1a>, <0x07>;
#phy
-cells = <0>;
status = "okay";
};
i2c0: i2c0@1f223000 {
compatible = "sstar,i2c";
reg = <0x1F223000 0x200>;
clock
-frequency = <200000>;
group = <0>;
//if u want set tSU/tHD, do not set 0, tSU = (t
-su
-* / i2c
-srcclk)S, tHD = (t
-hd
-* / i2c
-srcclk)S
t
-su
-sta = <0>;
t
-hd
-sta = <0>;
t
-su
-sto = <0>;
t
-hd
-sto = <0>;
//1
->open drain; 2
->open drain + one push; 3
->open drain + one push + clock push;
output
-mode = <2>;
status = "okay";
};
i2c1: i2c1@1f223200 {
compatible = "sstar,i2c";
reg = <0x1F223200 0x200>;
clock
-frequency = <200000>;
//dma
-enable;
group = <1>;
t
-su
-sta = <0>;
t
-hd
-sta = <0>;
t
-su
-sto = <0>;
t
-hd
-sto = <0>;
output
-mode = <2>;
status = "okay";
};
i2c2: i2c2@1f222E00 {
compatible = "sstar,i2c";
reg = <0x1F222E00 0x200>;
clock
-frequency = <200000>;
//dma
-enable;
group = <2>;
t
-su
-sta = <0>;
t
-hd
-sta = <0>;
t
-su
-sto = <0>;
t
-hd
-sto = <0>;
output
-mode = <2>;
status = "okay";
};
uart1: uart1@1F221200 {
compatible = "sstar,uart";
reg = <0x1F221200 0x200>;
status = "okay";
};
fuart: fuart@1F220400 {
compatible = "sstar,uart";
reg = <0x1F220400 0x200>;
status = "disabled";
};
uart2: uart2@1F221400 {
compatible = "sstar,uart";
reg = <0x1F221400 0x200>;
status = "okay";
};
spi0: spi0@1F222000 {
compatible = "sstar,mspi";
reg = <0x1F222000 0x200>;
mspi
-group = <0>;
use
-dma = <0>;
cs
-num = <2>;
//cs
-ext = <PAD_UNKNOWN>;
//4to3
-mode;
//clk
-out
-mode = <27000000>;
status = "okay";
};
fsp_qspi0: fsp_qspi@1F002C00 {
compatible = "sstar,fsp
-qspi";
reg = <0x1F002C00 0x200>, <0x1F002E00 0x200>;
cs
-num = <2>;
engine = <0>;
dma = <1>;
status = "okay";
};
};
};
&clks {
#address
-cells = <1>;
#size
-cells = <1>;
};
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