半加器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY h_adder IS
PORT(a,b:IN STD_LOGIC;
  so,co:OUT STD_LOGIC);
END h_adder;
ARCHITECTURE example2 OF h_adder IS
BEGIN
so<=a XOR b;
co<=a AND b;
END example2;