LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mul IS
PORT(a,b:IN integer range 0 to 255;
q:OUT integer range 0 to 65535);
END mul;
ARCHITECTURE one OF mul IS
BEGIN
q<=a*b;
END one;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mul IS
PORT(a,b:IN integer range 0 to 255;
q:OUT integer range 0 to 65535);
END mul;
ARCHITECTURE one OF mul IS
BEGIN
q<=a*b;
END one;