2选1数据选择器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux21 IS
PORT(a,b:IN STD_LOGIC;
  s:IN STD_LOGIC;
  y:OUT STD_LOGIC);
END mux21;
ARCHITECTURE example3 OF mux21 IS
BEGIN
y<=a WHEN s='0' ELSE b;
END example3;