module PCJump(
input wire[25:0] rst1,
input wire[3:0] rst2,
output reg[31:0] dst
);
always @(rst1,rst2,dst) begin
dst<={rst2,rst1,2'b00};
end
endmodule
cpu之PCJump
最新推荐文章于 2024-09-12 23:39:24 发布
module PCJump(
input wire[25:0] rst1,
input wire[3:0] rst2,
output reg[31:0] dst
);
always @(rst1,rst2,dst) begin
dst<={rst2,rst1,2'b00};
end
endmodule