Procedural Statements-各种功能模块简单说明(systemverilog)

Procedural statements are introduced by the following

initial // enable this statement at the beginning of simulation and execute it only once
final // do this statement once at the end of simulation
always, always_comb, always_latch, always_ff // loop forever
task // do these statements whenever the task is called
function // do these statements whenever the function is called and return a value

SystemVerilog adds C-like break, continue and return functionality, which do not require the use of block names.