Exams/2014 q3fsm

最新推荐文章于 2024-11-07 19:23:42 发布

Aullon Cheung

最新推荐文章于 2024-11-07 19:23:42 发布

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文章标签： fpga开发

本文链接：https://blog.youkuaiyun.com/aulloncheung/article/details/123379974

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本文探讨了一种使用有限状态机（FSM）解决的问题，该FSM根据输入w的特定模式设置输出z。FSM在输入s为0时保持在A状态，当s变为1时进入B状态。在B状态中，FSM在连续三个时钟周期内检查w，如果w在两个周期中有且仅有一个为1，则在下一个周期输出z为1，否则z为0。通过最少的状态设计，详细展示了如何利用w输入实现计数逻辑。

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题目：

Consider a finite state machine with inputs s and w. Assume that the FSM begins in a reset state called A, as depicted below. The FSM remains in state A as long as s = 0, and it moves to state B when s = 1. Once in state B the FSM examines the value of the input w in the next three clock cycles. If w = 1 in exactly two of these clock cycles, then the FSM has to set an output z to 1 in the following clock cycle. Otherwise z has to be 0. The FSM continues checking w for the next three clock cycles, and so on. The timing diagram below illustrates the required values of z for different values of w.

Use as few states as possible. Note that the s input is used only in state A, so you need to consider just the w input.

代码：

module top_module (
    input clk,
    input reset,   // Synchronous reset
    input s,
    input w,
    output z
);
    parameter A=0,B=1,C=2,D=3;
    reg [1:0] state,next;
    
    always @(posedge clk)
        if(reset)
            state <= A;
    	else
            state <= next;
    
    always @(*)
        case (state)
            A:next=s?B:A;
            B:next=C;
            C:next=D;
            D:next=B;
            default:next=A;
        endcase
    
    reg [2:0] w_reg;
    always @(*)
        case (state)
            B:w_reg[2]=w;
            C:w_reg[1]=w;
            D:w_reg[0]=w;
            default:w_reg=0;
        endcase
    
    always @(posedge clk)
        if(reset)
            z <= 0;
    	else
            case(next)
                A: z<=0;
                C: z<=0;
                D: z<=0;
                B:begin
                    case(w_reg)
                        3'b011:z<=1;
                        3'b101:z<=1;
                        3'b110:z<=1;
                        default:z<=0;
                    endcase
                end
            endcase

endmodule