FPGA出租车计费器的Verilog源代码

module fp50m(clk,reset,newclk,newclk1);

input clk,reset;output newclk,newclk1；

reg newclk,newclk1;reg [31:0] count,count1;

always@(posedge clk or negedge reset)

begin

if(!reset)

begin

newclk<=1'd0;

count<=32'd0;

end

else if(count==32'd25000000)

begin

count<=32'd0;

newclk<=~newclk;

end//end begin

else count<=count+1'd1;

end

always@(posedge clk or negedge reset)

begin

if(!reset)

begin

newclk1<='d0;

count1<=32'd0;

end

else if(count1==32'd100000)

begin

count1<=32'd0;

newclk1<=~newclk1;

end

else

count1<=count1+1'd1;

endendmodule

module distance(clk,start,reset,run,distance,distance_enable);

input clk,start,reset,run;

output [7:0] distance;

reg [7:0] distance;

output distance_enable;

reg distance_enable;

always@(posedge clk or negedge reset)

begin

if(!reset)

distance<=8'd0;

else if(!start) distance<=8'd0;

else

begin if (run)

begin if(distance[3:0]==9)//判断distance的低四位记到了9没

begin distance[3:0]<=4'd0;//记到则清零

if(distance[7:4]==9) //判断高四位记到9没

distance[7:4]<=4'd0;// 记到则清零

else distance[7:4]<=distance[7:4]+1'd1;// distance的高四位没有记到9则加1

end//end else

distance[3:0]<=distance[3:0]+1'd1;// distance的低四位没有记到9则加1

end//end always