Quartus Prime解决novopt错误

在使用Quartus Prime的过程中遇到了这个问题:

一开始以为是版本问题,Quartus Prime和modelsim不兼容,还重新下了,发现不是。同时也不是环境变量的问题。

最后发现好像是stimulate的过程中尝试使用novopt,但是所用的modelsim版本不支持,同时之后的新版本也弃用了,最后斟酌了半天解决了。

解决方式如下:

在setting里面把红色框的部分去掉就可以了,但是这个每次重新启动stimulate都需要删除掉,如果有更加好的解决方法欢迎讨论~觉得有帮助的就点个赞叭!

Determining the location of the ModelSim executable... Using: E:\intelFPGA\18.1\modelsim_ase\win32aloem To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. **** Generating the ModelSim Testbench **** quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off 1 -c 1 --vector_source="E:/intelFPGA/WORK/Waveform.vwf" --testbench_file="E:/intelFPGA/WORK/simulation/qsim/Waveform.vwf.vt" Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition Info: Copyright (C) 2018 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Thu May 22 00:35:13 2025 Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off 1 -c 1 --vector_source=E:/intelFPGA/WORK/Waveform.vwf --testbench_file=E:/intelFPGA/WORK/simulation/qsim/Waveform.vwf.vt Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Completed successfully. Completed successfully. **** Generating the functional simulation netlist **** quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="E:/intelFPGA/WORK/simulation/qsim/" 1 -c 1 Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition Info: Copyright (C) 2018 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Thu May 22 00:35:14 2025 Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=E:/intelFPGA/WORK/simulation/qsim/ 1 -c 1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file 1.vo in folder "E:/intelFPGA/WORK/simulation/qsim//" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 4725 megabytes Info: Processing ended: Thu May 22 00:35:15 2025 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Completed successfully. **** Generating the ModelSim .do script **** E:/intelFPGA/WORK/simulation/qsim/1.do generated. Completed successfully. **** Running the ModelSim simulation **** E:/intelFPGA/18.1/modelsim_ase/win32aloem/vsim -c -do 1.do Reading E:/intelFPGA/18.1/modelsim_ase/tcl/vsim/pref.tcl # 10.5b # do 1.do # ** Warning: (vlib-34) Library already exists at "work". # couldn't execute "E:\intelFPGA\18.1\modelsim_ase\win32aloem\vlog": invalid argument # couldn't execute "E:\intelFPGA\18.1\modelsim_ase\win32aloem\vlog": invalid argument # vsim -novopt -c -t 1ps -L cyclonev_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.1_vlg_vec_tst # Start time: 00:35:15 on May 22,2025 # ** Error: (vsim-3170) Could not find 'work.1_vlg_vec_tst'. # Searched libraries: # E:/intelFPGA/18.1/modelsim_ase/altera/verilog/cyclonev # E:/intelFPGA/18.1/modelsim_ase/altera/verilog/altera # E:/intelFPGA/18.1/modelsim_ase/altera/verilog/altera_mf # E:/intelFPGA/18.1/modelsim_ase/altera/verilog/220model # E:/intelFPGA/18.1/modelsim_ase/altera/verilog/sgate # E:/intelFPGA/18.1/modelsim_ase/altera/verilog/altera_lnsim # E:/intelFPGA/WORK/simulation/qsim/work # Error loading design Error loading design # End time: 00:35:16 on May 22,2025, Elapsed time: 0:00:01 # Errors: 1, Warnings: 0 Error.
最新发布
05-23
### 如何在Quartus II 11.0中执行仿真操作 #### 工具准备 为了能够在Quartus II 11.0环境中顺利进行仿真工作,用户需先完成Quartus II 11.0套件的下载与安装[^1]。此外,由于该版本取消了自带的Quartus II Simulator模拟器,因此建议搭配第三方工具如Altera-ModelSim来进行电路行为验证[^3]。 #### 创建项目并编写测试文件 启动Quartus II之后新建一个工程,在此过程中定义好目标器件以及设计输入方式(VHDL, Verilog HDL)。接着创建用于描述待测模块行为特性的Testbench源码文档,这一步骤至关重要因为它决定了后续仿真的准确性。 #### 配置编译选项 进入`Assignments -> Settings...`, 查找有关Simulation设置项下的EDA Tool Settings节点,指定选用的外部仿真程序为ModelSim-Altera Edition,并确认路径配置无误以便于两者间建立有效的通信连接[^2]。 #### 编写激励信号脚本 针对所要检验的功能逻辑部分精心构思一组或多组合理的输入序列作为刺激条件加载给DUT(Device Under Test),即被测实体。这些数据通常保存在一个独立的`.do`批处理命令文件里供调用执行。 ```tcl # Example of a Modelsim do file content vlib work vlog your_testbench_file.v vsim -novopt work.your_module_tb add wave /your_module_tb/* force {clk} 0 0ns, 1 {50 ns} -r 100 run 1000ns ``` #### 启动联合调试环境 当一切就绪后返回至Quartus主界面点击菜单栏中的`Tools->Run Simulation Tool->RTL Simulation`来触发整个流程。此时会自动跳转到已关联好的ModelSim窗口内继续剩余环节直至结束观察波形变化情况从而判断芯片内部运作是否符合预期效果。
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