--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {DaqMuxCtrlRamVhd} architecture {DaqMuxCtrlRamVhd}}
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DaqMuxCtrlRamVhd is
port(
-- Write interface
plWrEn : in std_logic;
puv9WrAdr : in unsigned( 8 downto 0 );
plv48WrData : in std_logic_vector( 47 downto 0 );
-- Read interface
puv9RdAdr : in unsigned( 8 downto 0 );
plv48RdData : out std_logic_vector( 47 downto 0 ) := ( others => '0' );
-- Clock, common to both read and write side
plClk : in std_logic
);
end DaqMuxCtrlRamVhd;
--}} End of automatically maintained section
architecture DaqMuxCtrlRamVhd of DaqMuxCtrlRamVhd is
-- This RAM controls:
-- 1) MUX channel select
-- 2) Result handler RAM addressing
-- The RAM holds a total of 160 MUX states/addresses (32 x 5)
-- 160 samples per ADC = 83.2 us = 1x 12kHz period (320 samples)
-- 40 samples per ADC = 20.8 us = 1x 48kHz period (80 samples)
-- 10 samples per ADC = 5.2 us = 1x 192kHz period (20 samples)
-- _________ _________ _________ _________
-- InvCurL1AFastSns-----------------|I0 MUX| | ADC| InvCurL1BFastSns-----------------|I0 MUX| | ADC|
-- Mains1CurL1AFastSns-----------------|I1 O|---|VA1 | Mains1CurL1BFastSns-----------------|I1 O|---|VB1 |
-- AdcMuxBit(6)-----------------|S MuxA1| | | AdcMuxBit(6)-----------------|S MuxB1| | |
-- ? | | ? | |
-- _________ | | _________ | |
-- InvCurL2AFastSns-----------------|I0 MUX| | | InvCurL2BFastSns-----------------|I0 MUX| | |
-- Mains1CurL2AFastSns-----------------|I1 O|---|VA2 | Mains1CurL2BFastSns-----------------|I1 O|---|VB2 |
-- AdcMuxBit(6)-----------------|S MuxA2| | | AdcMuxBit(6)-----------------|S MuxB2| | |
-- ? | | ? | |
-- _________ | | _________ | |
-- InvCurL3AFastSns-----------------|I0 MUX| | | InvCurL3BFastSns-----------------|I0 MUX| | |
-- Mains1CurL3AFastSns-----------------|I1 O|---|VA3 | Mains1CurL3BFastSns-----------------|I1 O|---|VB3 |
-- AdcMuxBit(7)-----------------|S MuxA3| | | AdcMuxBit(7)-----------------|S MuxB3| | |
-- ? | | ? | |
-- _________ | | _________ | |
-- BattCurNegAFastSns-----------------|I0 MUX| | | BattCurNegBFastSns-----------------|I0 MUX| | |
-- BattCurPosAFastSns-----------------|I1 O|---|VA4 | BattCurPosBFastSns-----------------|I1 O|---|VB4 |
-- AdcMuxBit(7)-----------------|S MuxA4| | | AdcMuxBit(7)-----------------|S MuxB4| | |
-- ? | | ? | |
-- _________ | | _________ | |
-- InvVolL1ASns-----------------|I0 MUX| | | InvVolL3ASns-----------------|I0 MUX| | |
-- Mains1VolL1Sns-----------------|I1 | | | Mains1VolL3Sns-----------------|I1 | | |
-- InvVolL1BSns-----------------|I2 | | | InvVolL3BSns-----------------|I2 | | |
-- Mains1VolL1PriSns-----------------|I3 | | | Mains1VolL3PriSns-----------------|I3 | | |
-- InvVolL1ASns-----------------|I4 | | | InvVolL3ASns-----------------|I4 | | |
-- Mains1VolL1Sns-----------------|I5 | | | Mains1VolL3Sns-----------------|I5 | | |
-- InvVolL1BSns-----------------|I6 | | | InvVolL3BSns-----------------|I6 | | |
-- _________ | | | DOUTA|---AdcDataA _________ | | | DOUTB|---AdcDataB
-- OutVolL1Sns---|I0 MUX| | | | | OutVolL3Sns---|I0 MUX| | | | |
-- AdcAVolRefSns---|I1 O|---|I7 O|---|VA5 | AdcBVolRefSns---|I1 O|---|I7 O|---|VB5 |
-- AdcMuxBit(8)---|S MuxA7| | | | | AdcMuxBit(8)---|S MuxB7| | | | |
-- ? | | | | ? | | | |
-- | | | | | | | |
-- AdcMuxBit(3)-----------------|S0 | | | AdcMuxBit(3)-----------------|S0 | | |
-- AdcMuxBit(4)-----------------|S1 | | | AdcMuxBit(4)-----------------|S1 | | |
-- AdcMuxBit(5)-----------------|S2 MuxA5| | | AdcMuxBit(5)-----------------|S2 MuxB5| | |
-- ? | | ? | |
-- _________ | | _________ | |
-- InvVolL2ASns-----------------|I0 MUX| | | BattVolPosPriSns-----------------|I0 MUX| | |
-- Mains1VolL2Sns-----------------|I1 | | | BattVolPosSns-----------------|I1 | | |
-- InvVolL2BSns-----------------|I2 | | | DcBusVolPosASns-----------------|I2 | | |
-- Mains1VolL2PriSns-----------------|I3 | | | BattVolNegPriSns-----------------|I3 | | |
-- InvVolL2ASns-----------------|I4 | | | BattVolNegSns-----------------|I4 | | |
-- Mains1VolL2Sns-----------------|I5 | | | DcBusVolNegASns-----------------|I5 | | |
-- InvVolL2BSns-----------------|I6 | | | DcBusVolAvgBSns-----------------|I6 | | |
-- OutVolL2Sns-----------------|I7 O|---|VA6 | HsTempSns-----------------|I7 O|---|VB6 |
-- | | | | | | | |
-- AdcMuxBit(3)-----------------|S0 | | | AdcMuxBit(3)-----------------|S0 | | |
-- AdcMuxBit(4)-----------------|S1 | | | AdcMuxBit(4)-----------------|S1 | | |
-- AdcMuxBit(5)-----------------|S2 MuxA6| | | AdcMuxBit(5)-----------------|S2 MuxB6| | |
-- ? | | ? | |
-- AdcMuxBit(0)-------------------------------|S0 | AdcMuxBit(0)-------------------------------|S0 |
-- AdcMuxBit(1)-------------------------------|S1 | AdcMuxBit(1)-------------------------------|S1 |
-- AdcMuxBit(2)-------------------------------|S2 | AdcMuxBit(2)-------------------------------|S2 |
-- ? ?
-- This block RAM controls 9 ADC mux addressing signals and 8 Result Handler address bits
-- Nibble no RAM bits HW mux signals Description
-- --------- -------- -------------- -----------
-- 0 RamBits[2:0] ADC_MUX_BIT[2:0] ADC build-in mux
-- 1 RamBits[6:4] ADC_MUX_BIT[5:3] Slow channel mux
-- 2 RamBits[8] ADC_MUX_BIT[6] Fast current channel L1, L2 mux
-- 3 RamBits[12] ADC_MUX_BIT[7] Fast current channel L3, batt mux
-- 4 RamBits[16] ADC_MUX_BIT[8] Slow cascaded channel mux
-- 5 RamBits[23:20] Unused
-- 6 RamBits[24] FastCurSnsInvertAdcA
-- 7 RamBits[28] FastCurSnsInvertAdcB
-- 8+9 RamBits[39:32] CalibrationRamRdAdr[7:0]
-- 10+11 RamBits[47:40] ResultHandlerRamWrAdr[7:0]
-- Below 6 fast current sensors are inverted in the hardware, which must be compensated for in the FPGA,
-- for each of these samples the "FastCurSnsInvert" flag is asserted:
-- InvCurL3A
-- InvCurL1B
-- InvCurL2B
-- InvCurL3B
-- Mains1CurL3A
-- Mains1CurL2B
-- Note! ResultHandlerAdr and MuxCtrl are offset one sample (520 ns) in order to compensate
-- for ADC result communication delay.
-- Dual port RAM type definition
-- RAM size = 512 * 48 = 24,576 [bits] = 3072 [bytes] = 3 * M10K block RAM's
type alv48MuxCtrlRam_t is array( 0 to 159 ) of std_logic_vector( 47 downto 0 );
-- Dual port RAM signal definition
-- Used addresses = 160
-- Mux duration = 160 * 520 ns = 83.2 us (12 kHz)
signal salv48MuxCtrlRam : alv48MuxCtrlRam_t :=
(
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
--12 kHz
-- TODO: calibration wr/rd address未定
-- 整PFC电流和逆变电流的采样顺序,先采样PFC电流
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
X"DF_03_10_0_01140", X"40_04_10_0_01141", X"50_05_10_0_01042", X"60_02_10_0_01043", X"70_16_11_0_00040", X"00_00_11_0_00041", X"10_01_11_0_00142", X"20_02_10_0_00143", -- FAST currents
X"30_07_00_0_00044", -- InvVolL3A[0] / InvVolL1A[0]
X"88_0B_00_0_00045", -- BattVolPriSns / InvVolL2A[0]
X"90_03_10_0_01110", X"41_04_10_0_01111", X"51_05_10_0_01012", X"61_02_10_0_01013", X"71_16_11_0_00010", X"01_00_11_0_00011", X"11_01_11_0_00112", X"21_02_10_0_00113", -- FAST currents
X"31_07_00_0_00014", -- Mains1VolL3[0] / Mains1VolL1[0]
X"80_0B_00_0_00015", -- BattVolPosSns[0] / Mains1VolL2[0]
X"84_03_10_0_01120", X"42_04_10_0_01121", X"52_05_10_0_01022", X"62_02_10_0_01023", X"72_16_11_0_00020", X"02_00_11_0_00021", X"12_01_11_0_00122", X"22_02_10_0_00123", -- FAST currents
X"32_07_00_0_00024", -- InvVolL3B[0] / InvVolL1B[0]
X"8C_0B_00_0_00025", -- BattVolNegSns[0] / InvVolL2B[0]
X"94_03_10_0_01130", X"43_04_10_0_01131", X"53_05_10_0_01032", X"63_02_10_0_01033", X"73_16_11_0_00030", X"03_00_11_0_00031", X"13_01_11_0_00132", X"23_02_10_0_00133", -- FAST currents
X"33_07_00_0_00034", -- Mains1VolL3Pri[0] / Mains1VolL1Pri[0]
X"98_0B_00_0_00035", -- BattVolNegPriSns[0] / Mains1VolL2Pri[0]
X"99_03_10_0_01140", X"44_04_10_0_01141", X"54_05_10_0_01042", X"64_02_10_0_01043", X"74_16_11_0_00040", X"04_00_11_0_00041", X"14_01_11_0_00142", X"24_02_10_0_00143", -- FAST currents
X"34_07_00_0_00044", -- InvVolL3A[1] / InvVolL1A[1]
X"89_0B_00_0_00045", -- DC_BUS_VOL_POS_A_SNS / InvVolL2A[1]
X"91_03_10_0_01150", X"45_04_10_0_01151", X"55_05_10_0_01052", X"65_02_10_0_01053", X"75_16_11_0_00050", X"05_00_11_0_00051", X"15_01_11_0_00152", X"25_02_10_0_00153", -- FAST currents
X"35_07_00_0_00054", -- Mains1VolL3[1] / Mains1VolL1[1]
X"81_0B_00_0_00055", -- DcBusVolNegASns / Mains1VolL2[1]
X"85_03_10_0_01160", X"46_04_10_0_01161", X"56_05_10_0_01062", X"66_02_10_0_01063", X"76_16_11_0_00060", X"06_00_11_0_00061", X"16_01_11_0_00162", X"26_02_10_0_00163", -- FAST currents
X"36_07_00_0_00064", -- InvVolL3B[1] / InvVolL1B[1]
X"8D_0B_00_0_00065", -- DC_BUS_VOL_SUM_B_SNS / InvVolL2B[1]
X"91_03_10_0_01170", X"47_04_10_0_01171", X"57_05_10_0_01072", X"67_02_10_0_01073", X"77_16_11_0_00070", X"07_00_11_0_00071", X"17_01_11_0_00172", X"27_02_10_0_00173", -- FAST currents
X"37_07_00_0_00074", -- OutVolL3[0] / OutVolL1[0]
X"9A_0B_00_0_00075", -- PM_ID_SAMPLE / OutVolL2[0]
X"9B_03_10_0_01140", X"48_04_10_0_01141", X"58_05_10_0_01042", X"68_02_10_0_01043", X"78_16_11_0_00040", X"08_00_11_0_00041", X"18_01_11_0_00142", X"28_02_10_0_00143", -- FAST currents
X"38_07_00_0_00044", -- InvVolL3A[2] / InvVolL1A[2]
X"8A_0B_00_0_00045", -- null / InvVolL2A[2]
X"92_03_10_0_01110", X"49_04_10_0_01111", X"59_05_10_0_01012", X"69_02_10_0_01013", X"79_16_11_0_00010", X"09_00_11_0_00011", X"19_01_11_0_00112", X"29_02_10_0_00113", -- FAST currents
X"39_07_00_0_00014", -- Mains1VolL3[2] / Mains1VolL1[2]
X"82_0B_00_0_00015", -- null / Mains1VolL2[2]
X"86_03_10_0_01120", X"4A_04_10_0_01121", X"5A_05_10_0_01022", X"6A_02_10_0_01013", X"7A_16_11_0_00020", X"0A_00_11_0_00021", X"1A_01_11_0_00122", X"2A_02_10_0_00123", -- FAST currents
X"3A_07_00_0_00024", -- InvVolL3B[2] / InvVolL1B[2]
X"8E_0B_00_0_00025", -- null / InvVolL2B[2]
X"96_03_10_0_01130", X"4B_04_10_0_01131", X"5B_05_10_0_01032", X"6B_02_10_0_01033", X"7B_16_11_0_00030", X"0B_00_11_0_00031", X"1B_01_11_0_00132", X"2B_02_10_0_00133", -- FAST currents
X"3B_07_00_0_00024", -- NULL
X"DF_0B_00_0_00025", -- null
X"DF_03_10_0_01140", X"4C_04_10_0_01141", X"5C_05_10_0_01042", X"6C_02_10_0_01043", X"7C_16_11_0_00040", X"0C_00_11_0_00041", X"1C_01_11_0_00142", X"2C_02_10_0_00143", -- FAST currents
X"3C_07_00_0_00044", -- InvVolL3A[3] / InvVolL1A[3]
X"8B_0B_00_0_00045", -- null / InvVolL2A[3]
X"93_03_10_0_01150", X"4D_04_10_0_01151", X"5D_05_10_0_01052", X"6D_02_10_0_01053", X"7D_16_11_0_00050", X"0D_00_11_0_00051", X"1D_01_11_0_00152", X"2D_02_10_0_00153", -- FAST currents
X"3D_07_00_0_00054", -- Mains1VolL3[3] / Mains1VolL1[3]
X"83_0B_00_0_00055", -- null / Mains1VolL2[3]
X"87_03_10_0_01160", X"4E_04_10_0_01161", X"5E_05_10_0_01062", X"6E_02_10_0_01063", X"7E_16_11_0_00060", X"0E_00_11_0_00061", X"1E_01_11_0_00162", X"2E_02_10_0_00163", -- FAST currents
X"3E_07_00_0_00064", -- InvVolL3B[3] / InvVolL1B[3]
X"8F_0B_00_0_00065", -- null / InvVolL2B[3]
X"97_03_10_0_01170", X"4F_04_10_0_01171", X"5F_05_10_0_01072", X"6F_02_10_0_01073", X"7F_16_11_0_00070", X"0F_00_11_0_00071", X"1F_01_11_0_00172", X"2F_02_10_0_00173", -- FAST currents
X"3F_07_00_0_10074", -- AdcBVolRefSns_2.5V / AdcAVolRefSns_2.5V
X"9C_14_00_0_10075" -- null / NILL
);
attribute ramstyle : string;
attribute ramstyle of salv48MuxCtrlRam : signal is "M10K";
begin
WriteProcess : process( plClk )
begin
if rising_edge( plClk ) then
if plWrEn = '1' then
salv48MuxCtrlRam( to_integer( puv9WrAdr )) <= plv48WrData;
end if;
end if;
end process WriteProcess;
ReadProcess : process( plClk )
begin
if rising_edge( plClk ) then
plv48RdData <= salv48MuxCtrlRam( to_integer( puv9RdAdr ));
end if;
end process ReadProcess;
end DaqMuxCtrlRamVhd;
请解析以上VHDL代码