【System Verilog and UVM基础入门4】phase机制

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分类专栏：汽车芯片IC验证文章标签： arm开发硬件工程

于 2023-08-08 16:36:44 首次发布

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本文介绍了System Verilog和UVM中的phase机制，它是仿真生命周期中的同步工具。所有组件都经历预定义的phase，不能进入下一个phase直到当前phase执行完毕。phase分为构建、运行和清理三个阶段，并详细阐述了主要的UVM Phases及其作用。此外，还强调了run_phase与其他run-time phases的并行关系以及如何创建自定义phase。

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1. phase机制

1.1 Main UVM Phases

1.2 Phase Definition

1. phase机制

All testbench components are derived from uvm_componentand are aware of the phase concept. Each component goes through a pre-defined set of phases, and it cannot proceed to the next phase until all components finish their execution inthe current phase. So UVM phases act as a synchronizing mechanism in the life cycle of a simulation.

Because phases are defined as callbacks, classes derived from uvm_component can perform useful work in the callback phase method. Methods that do not consume simulation time are function s and meth

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