PCIE设备树解析

最新推荐文章于 2025-07-19 08:45:00 发布

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最新推荐文章于 2025-07-19 08:45:00 发布 · 3.4k 阅读

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#驱动开发 #linux #嵌入式硬件

本文详细解析了RK3588芯片中PCIe2.0RC控制器的DTS配置，重点讨论了bus-range字段定义的总线号范围以及ranges字段中的PCI和CPU地址空间分配。

下面是一段RK3588的PCIE2.0 的RC控制器的DTS配置，我们针对每个配置进行简要说明

pcie2x1l1: pcie@fe180000 {
   
   
	compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
	#address-cells = <3>;
	#size-cells = <2>;
	bus-range = <0x30 0x3f>;
	clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
		 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
		 <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;
	clock-names = "aclk_mst", "aclk_slv",
		      "aclk_dbi", "pclk",
		      "aux", "pipe";
	device_type = "pci";
	interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH