June 25th Monday (六月 二十五日 月曜日)

   At ARM chip when more than one exception occur, how to deal with them? Or is there
a sequence of deal with exceptions?  Yes, there is a priority of deal with that similar
situtation.

  There is a table following.  It list the priority of exceptions.

1(the highest level)          reset
2                               abt (data)
3                               fiq
4                               iqr
5                               abt (instrucion)
6(the lowest level)             und, swi

  Jump Instructions

  There are two ways to implement a instruction flow jumping.
  1) to use specified instructions;
  2) to put a address into the PC register.

  In the second way, you can implement jump out any where in a 4GB space.  Before jumping
out, you can use the instructions, such as MOV LR, PC, to save a return address, in order
to implement invoke a sub-procedure in 4GB liner address space.

  ARM instruct set supplies 4 jump instructions:

1. B
   B{conditon} destination
   It is the simplest jumping instruction.  Meetting it, ARM chip immediately jump to the
"destination".  Notice that the value in the "B" instruction is not an absoluate addressing
but an relative addressing to PC register.

  B Label
  CMP R1, #0
  BEQ Label

2. BL
   BL{conditon} destination
   Before jumping, the content of PC can be saved into the R14 register.  So, it can be used
to implement invoking a sub procedure and return from that sub procedure.

3. BLX
   BLX destination
   Before jumping, change the status of chip from ARM into Thumb, at once the content of PC is
saved into the R14 register.  When a sub procedure use Thumb instructions, a caller use ARM
instructions, the "BLX" implement to switch the status between them.  It is a bridge between these
two statuses.

4. BX
   BX destination
   It just jump to a specified address at where is an ARM instruction or a Thumb instruction.