module Cordic(
clk,
rst_n,
deg,
sin,
cos,
finish
);
input clk;
input rst_n;
input signed [49:0]deg;//Q40 1符号位 9整数位
output reg [31:0]sin;//Q31
output reg [31:0]cos;
output reg finish;
reg signed [31:0]x;
reg signed [31:0]y;
reg signed [49:0]z;
reg [3:0] quadrant;
localparam signed [49:0]DEG90=50'h05a00000000a0;
localparam signed [49:0]DEG180=50'h0b40000000140;
localparam signed [49:0]DEG270=50'h10dfffff860c0;
localparam signed [49:0]DEG360=50'h1680000000280;
localparam signed [32:0]KN=32'h4dba76d6;
reg signed [49:0]deglis[15:0];
always@(posedge clk)begin
deglis[0]<=50'h02cffffff3d00;
deglis[1]<=50'h01a90a7323be0;
deglis[2]<=50'h00e09474070a0;
deglis[3]<=50'h0072001123b80;
deglis[4]<=50'h003938aa64bb0;
deglis[5]<=50'h001ca3794f310;
deglis[6]<=50'h000e52a1ab098;
deglis[7]<=50'h0007296d7a290;
deglis[8]<=50'h000394ba51d40;
deglis[9]<=50'h0001ca5d9b6a8;
deglis[10]<=50'h0000e52edc0a0;
deglis[11]<=50'h000072976fd38;
deglis[12]<=50'h0000394bb8220;
deglis[13]<=50'h00001ca5dc16a;
deglis[14]<=50'h00000e52ee0ce;
deglis[15]<=50'h000007297706c;
end
//调整象限
always@(*)begin
if(!deg[49])begin
if((deg>=0)&&(deg<DEG90))begin
z=deg;
quadrant=1;
end
else if((deg>=DEG90)&&(deg<DEG180))begin
z=deg-DEG90;
quadrant=2;
end
else if((deg>=DEG180)&&(deg<DEG270))begin
z=DEG270-deg;
quadrant=3;
end
else if((deg>=DEG270)&&(deg<DEG360))begin
z=deg-DEG360;
quadrant=4;
end
end
else if(deg[49])begin
if((deg[48:0]>=0)&&(deg[48:0]<DEG90[48:0]))begin
z={1'b0,deg[48:0]};
quadrant=4;
end
else if((deg[48:0]>=DEG90[48:0])&&(deg[48:0]<DEG180[48:0]))begin
z={1'b0,deg[48:0]}-DEG90;
quadrant=3;
end
else if((deg[48:0]>=DEG180[48:0])&&(deg[48:0]<DEG270[48:0]))begin
z=DEG270-{1'b0,deg[48:0]};
quadrant=2;
end
else if((deg[48:0]>=DEG270[48:0])&&(deg[48:0]<DEG360[48:0]))begin
z={1'b0,deg[48:0]}-DEG360;
quadrant=1;
end
end
end
reg [3:0] iter;
always@(posedge clk or negedge rst_n)
if(!rst_n)
iter<=0;
else if(!finish)
iter<=iter+1;
always@(posedge clk or negedge rst_n)
if(!rst_n)begin
sin<=0;
cos<=0;
end
else if(iter==15)begin
case(quadrant)
1:begin sin<=y;cos<=x;sin[31]<=0;cos[31]<=0;end
2:begin cos<=y;sin<=x;sin[31]<=0;cos[31]<=1;end
3:begin cos<=y;sin<=x;sin[31]<=1;cos[31]<=1;end
4:begin sin<=y;cos<=x;sin[31]<=1;cos[31]<=0;end
endcase
end
always@(posedge clk or negedge rst_n)
if(!rst_n)
finish<=0;
else if(iter==15)
finish<=1;
always@(posedge clk or negedge rst_n)
if(!rst_n)begin
x<=KN;
y<=0;
end
else if(!finish)
if(z[49]==0)begin
x<=x-(y>>>iter);
y<=y+(x>>>iter);
z<=z-deglis[iter];
end
else begin
x<=x+(y>>>iter);
y<=y-(x>>>iter);
z<=z+deglis[iter];
end
else begin
x<=x;
y<=y;
z<=z;
end
endmodule
fpga cordic
于 2023-10-26 20:40:19 首次发布