MSP430(G2553)用看门狗定时器来产生周期信号

最新推荐文章于 2021-11-25 23:03:44 发布

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最新推荐文章于 2021-11-25 23:03:44 发布

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分类专栏： C/C++ MSP430 文章标签： timer vector include module ie

本文链接：https://blog.youkuaiyun.com/KISSMonX/article/details/7972911

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#include <msp430g2553.h>
#include <intrinsics.h>


volatile unsigned int i = 0;  // 中断服务子程序中所用到的全局变量, 最好定义成 volatile 型, 具体原因和用法可以参考我的其他博文介绍

void main (void)
{
    WDTCTL = WDT_MDLY_0_5; // 周期 0.5ms, 设置可参考下面头文件中的截段
    IE1 |= WDTIE;          // 使能WDT中断
    P2DIR |= BIT2;         // P2.2输出
    _EINT();               // 使能全局中断
    for (;;)
    {
        LPM0;              // 进入LPM0
        _NOP();
    }
}


// 看门狗中断服务子程序
#pragma vector=WDT_VECTOR
__interrupt void WDT_Timer_ISR(void)
{
    if (i++ > 1) {
        P2OUT ^= BIT2;     // 取反
    }
}

==============================================================================================================================

//==========================================================================================================================
// 相关头文件中的定义
/************************************************************
* WATCHDOG TIMER
************************************************************/
#define __MSP430_HAS_WDT__             /* Definition to show that Module is available */

#define WDTCTL_             (0x0120u)  /* Watchdog Timer Control */
DEFW(   WDTCTL            , WDTCTL_)
/* The bit names have been prefixed with "WDT" */
#define WDTIS0              (0x0001u)
#define WDTIS1              (0x0002u)
#define WDTSSEL             (0x0004u)
#define WDTCNTCL            (0x0008u)
#define WDTTMSEL            (0x0010u)
#define WDTNMI              (0x0020u)
#define WDTNMIES            (0x0040u)
#define WDTHOLD             (0x0080u)
#define WDTPW               (0x5A00u)


/* WDT-interval times [1ms] coded with Bits 0-2 */
/* WDT is clocked by fSMCLK (assumed 1MHz) */
#define WDT_MDLY_32         (WDTPW+WDTTMSEL+WDTCNTCL)                         /* 32ms interval (default) */
#define WDT_MDLY_8          (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0)                  /* 8ms     " */
#define WDT_MDLY_0_5        (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1)                  /* 0.5ms   " */
#define WDT_MDLY_0_064      (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0)           /* 0.064ms " */
/* WDT is clocked by fACLK (assumed 32KHz) */
#define WDT_ADLY_1000       (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL)                 /* 1000ms  " */
#define WDT_ADLY_250        (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0)          /* 250ms   " */
#define WDT_ADLY_16         (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1)          /* 16ms    " */
#define WDT_ADLY_1_9        (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0)   /* 1.9ms   " */
/* Watchdog mode -> reset after expired time */
/* WDT is clocked by fSMCLK (assumed 1MHz) */
#define WDT_MRST_32         (WDTPW+WDTCNTCL)                                  /* 32ms interval (default) */
#define WDT_MRST_8          (WDTPW+WDTCNTCL+WDTIS0)                           /* 8ms     " */
#define WDT_MRST_0_5        (WDTPW+WDTCNTCL+WDTIS1)                           /* 0.5ms   " */
#define WDT_MRST_0_064      (WDTPW+WDTCNTCL+WDTIS1+WDTIS0)                    /* 0.064ms " */
/* WDT is clocked by fACLK (assumed 32KHz) */
#define WDT_ARST_1000       (WDTPW+WDTCNTCL+WDTSSEL)                          /* 1000ms  " */
#define WDT_ARST_250        (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0)                   /* 250ms   " */
#define WDT_ARST_16         (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1)                   /* 16ms    " */
#define WDT_ARST_1_9        (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0)            /* 1.9ms   " */