(* DowngradeIPIdentifiedWarnings=“yes“ *)

(* DowngradeIPIdentifiedWarnings="yes" *) 是一个 VHDL/Verilog 属性声明,通常用于 Xilinx Vivado 或 Xilinx ISE 设计工具中,主要用于处理 IP 核(Intellectual Property Core)的警告信息。


1. 作用

  • 当 Vivado 检测到 IP 核的版本或标识与当前项目不匹配时,会生成 IP_Identified 警告。

  • 这个属性告诉工具:“降低(忽略或减少)IP 标识相关的警告”,避免这些警告干扰编译过程。


2. 常见场景

  • 在实例化一个 Xilinx IP 核(如 FIFO、Block RAM、DSP 等)时,如果 IP 核是用较旧版本的 Vivado 生成的,新版本工具可能会发出警告。

  • 为了保持代码兼容性,设计者可以添加此属性,使工具不再报告这些警告。


3. 代码中的位置

通常放在模块实例化之前,作为修饰属性使用。

Verilog 示例:

(* DowngradeIPIdentifiedWarnings="yes" *)
your_ip_instance u1 (
    .clk(clk),
    .reset(reset),
    // ... 其他端口
);

VHDL 示例:

attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of your_ip_instance: label is "yes";

4. 类似属性

  • (* X_CORE_INFO = "..." *):提供 IP 核的版本信息。

  • (* CHECK_LICENSE_TYPE = "..." *):指定许可证类型。

  • (* CORE_GENERATION_INFO = "..." *):核心生成信息。


5. 注意事项

  • 这个属性主要用于 Xilinx 工具链,其他厂商(如 Intel Quartus)可能不支持。

  • 如果希望看到所有警告,可以设为 "no" 或直接删除该属性。


总结:
这是一个 Xilinx 专用的属性,用于抑制 IP 核版本标识不匹配的警告,使编译过程更干净。

module TOP( //BASIC Signal SYSCLK2_N, SYSCLK2_P, PCIE_PERSTN, QSFP28_0_STATUS_LEDY, QSFP28_0_STATUS_LEDG, QSFP28_0_ACTIVITY_LED, HBM_CATTRIP,//can't chang anymore //ethernet io QSFP28_0_RX_P, QSFP28_0_RX_N, QSFP28_0_TX_P, QSFP28_0_TX_N, SYNCE_CLK_N, SYNCE_CLK_P ); input wire SYSCLK2_N; input wire SYSCLK2_P; input wire PCIE_PERSTN; output reg QSFP28_0_STATUS_LEDY; //little yellow output reg QSFP28_0_STATUS_LEDG; //little green output reg QSFP28_0_ACTIVITY_LED; //big green output wire HBM_CATTRIP; //ETHERNET IO input wire QSFP28_0_RX_P; input wire QSFP28_0_RX_N; output wire QSFP28_0_TX_P; output wire QSFP28_0_TX_N; input wire SYNCE_CLK_N; input wire SYNCE_CLK_P; assign HBM_CATTRIP = 1'b0;//can't chang anymore must be 0 anymore wire SYSCLK2_100Mhz_i; IBUFDS #( .DIFF_TERM("TRUE"), .IOSTANDARD("LVDS") ) clk_buf ( .I (SYSCLK2_P), .IB (SYSCLK2_N), .O (SYSCLK2_100Mhz_i) ); wire SYSCLK2_100Mhz; BUFG clk_bufg ( .I (SYSCLK2_100Mhz_i), .O (SYSCLK2_100Mhz) ); wire rst_async_n = PCIE_PERSTN; // high = reset released reg [1:0] rst_sync; always @(posedge SYSCLK2_100Mhz or negedge rst_async_n) begin if (!rst_async_n) rst_sync <= 2'b00; else rst_sync <= {rst_sync[0], 1'b1}; end wire sys_rst_n = rst_sync[1]; reg [27:0] counter; always @(posedge SYSCLK2_100Mhz or negedge sys_rst_n) begin if (~sys_rst_n) begin counter <= 0; end else if(counter == 10000000) begin counter <= 0; end else begin counter <= counter + 1; end end wire sys_reset; wire restart_tx_rx_0;//reset wire send_continous_pkts_0; wire dclk; wire rx_gt_locked_led_0; wire rx_block_lock_led_0; reg [1:0]rx_gt_locked_led_0_SYSCLK2; reg [1:0]rx_block_lock_led_0_SYSCLK2; assign restart_tx_rx_0 = 1'b0; assign send_continous_pkts_0 = 1'b0; assign dclk = SYSCLK2_100Mhz; assign sys_reset = ~sys_rst_n; // active-high reset (* DowngradeIPIdentifiedWarnings="yes" *) xxv_ethernet_0_exdes xxv_rthernet_ip( .gt_rxp_in (QSFP28_0_RX_P), //I .gt_rxn_in (QSFP28_0_RX_N), //I .gt_txp_out (QSFP28_0_TX_P), //O .gt_txn_out (QSFP28_0_TX_N), //O .restart_tx_rx_0 (restart_tx_rx_0), //I .send_continous_pkts_0 (send_continous_pkts_0), //I .rx_gt_locked_led_0 (rx_gt_locked_led_0), //O .rx_block_lock_led_0 (rx_block_lock_led_0), //O .stat_reg_compare (), //O .sys_reset (sys_reset), //I .gt_refclk_p (SYNCE_CLK_P), //I .gt_refclk_n (SYNCE_CLK_N), //I .dclk (dclk) ); always @(posedge SYSCLK2_100Mhz or negedge sys_rst_n) begin if (~sys_rst_n) begin rx_gt_locked_led_0_SYSCLK2 <= 2'b0; end else begin rx_gt_locked_led_0_SYSCLK2[0] <= rx_gt_locked_led_0; rx_gt_locked_led_0_SYSCLK2[1] <= rx_gt_locked_led_0_SYSCLK2[0]; end end always @(posedge SYSCLK2_100Mhz or negedge sys_rst_n) begin if (~sys_rst_n) begin rx_block_lock_led_0_SYSCLK2 <= 2'b0; end else begin rx_block_lock_led_0_SYSCLK2[0] <= rx_block_lock_led_0; rx_block_lock_led_0_SYSCLK2[1] <= rx_block_lock_led_0_SYSCLK2[0]; end end always @(posedge SYSCLK2_100Mhz or negedge sys_rst_n) begin if (~sys_rst_n) begin QSFP28_0_ACTIVITY_LED <= 0; end else if(counter == 10000000) begin QSFP28_0_ACTIVITY_LED <= ~QSFP28_0_ACTIVITY_LED; end else begin QSFP28_0_ACTIVITY_LED <= QSFP28_0_ACTIVITY_LED; end end always @(posedge SYSCLK2_100Mhz or negedge sys_rst_n)begin if (~sys_rst_n) begin QSFP28_0_STATUS_LEDG <= 0; end else if(rx_gt_locked_led_0_SYSCLK2[1] == 1'b1)begin if(counter == 10000000)begin QSFP28_0_STATUS_LEDG <= ~QSFP28_0_STATUS_LEDG; end else begin QSFP28_0_STATUS_LEDG <= QSFP28_0_STATUS_LEDG; end end else begin QSFP28_0_STATUS_LEDG <= 0; end end always @(posedge SYSCLK2_100Mhz or negedge sys_rst_n)begin if (~sys_rst_n) begin QSFP28_0_STATUS_LEDY <= 0; end else if(rx_block_lock_led_0_SYSCLK2[1] == 1'b1)begin if(counter == 10000000)begin QSFP28_0_STATUS_LEDY <= ~QSFP28_0_STATUS_LEDY; end else begin QSFP28_0_STATUS_LEDY <= QSFP28_0_STATUS_LEDY; end end else begin QSFP28_0_STATUS_LEDY <= 0; end end endmodule
08-19
//----------------------------------------------------------------------------- // // (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //----------------------------------------------------------------------------- // // Project : UltraScale+ FPGA PCI Express v4.0 Integrated Block // File : cgator_wrapper.v // Version : 1.3 //----------------------------------------------------------------------------- //----------------------------------------------------------------------------- // // Project : Ultrascale FPGA Gen4 Integrated Block for PCI Express // File : cgator_wrapper.v // Version : 1.0 //----------------------------------------------------------------------------- `timescale 1ns/1ns (* DowngradeIPIdentifiedWarnings = "yes" *) module cgator_wrapper #( // Configurator parameters parameter PCIE_LOCATION = "X0Y0", parameter TCQ = 1, parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "TRUE", parameter PIPE_SIM_MODE = "FALSE", parameter EXTRA_PIPELINE = 1, parameter ROM_FILE = "cgator_cfg_rom.data", parameter ROM_SIZE = 32, parameter [15:0] REQUESTER_ID = 16'h10EE, parameter PCIE_EXT_CLK = "FALSE", // Use External Clocking Module parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h4, // 1- GEN1, 2 - GEN2, 4 - GEN3 parameter [4:0] PL_LINK_CAP_MAX_LINK_WIDTH = 5'h8, // 1- X1, 2 - X2, 4 - X4, 8 - X8 parameter PL_DISABLE_EI_INFER_IN_L0 = "TRUE", parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE", // USER_CLK[1/2]_FREQ :[0] = Disable user clock; [1] = 31.25 MHz; [2] = 62.50 MHz (default); [3] = 125.00 MHz; [4] = 250.00 MHz; [5] = 500.00 MHz; parameter integer USER_CLK2_FREQ = 2, parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz parameter AXISTEN_IF_RQ_PARITY_CHECK = "FALSE", parameter AXI4_CQ_TUSER_WIDTH = 88, parameter AXI4_CC_TUSER_WIDTH = 33, parameter AXI4_RQ_TUSER_WIDTH = 62, parameter AXI4_RC_TUSER_WIDTH = 75, parameter C_DATA_WIDTH = 64, parameter KEEP_WIDTH = C_DATA_WIDTH / 32 ) ( //------------------------------------------------------- // 0. Configurator I/Os //------------------------------------------------------- input start_config, output finished_config, output failed_config, //------------------------------------------------------- // 1. PCI Express (pci_exp) Interface //------------------------------------------------------- output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pci_exp_txp, output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pci_exp_txn, input [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pci_exp_rxp, input [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pci_exp_rxn, //------------------------------------------------------- // 2. Transaction (AXIS) Interface //------------------------------------------------------- output user_clk_out, output user_reset_out, output user_lnk_up, output phy_rdy_out, //------------------------------------------------------- output s_axis_rq_tready, input [C_DATA_WIDTH-1:0] s_axis_rq_tdata, input [KEEP_WIDTH-1:0] s_axis_rq_tkeep, input [AXI4_RQ_TUSER_WIDTH-1:0] s_axis_rq_tuser, input s_axis_rq_tlast, input s_axis_rq_tvalid, //------------------------------------------------------- output [C_DATA_WIDTH-1:0] m_axis_rc_tdata, output [KEEP_WIDTH-1:0] m_axis_rc_tkeep, output m_axis_rc_tlast, output m_axis_rc_tvalid, output [AXI4_RC_TUSER_WIDTH-1:0] m_axis_rc_tuser, input m_axis_rc_tready, //------------------------------------------------------- output wire [C_DATA_WIDTH-1:0] m_axis_cq_tdata, output wire [AXI4_CQ_TUSER_WIDTH-1:0] m_axis_cq_tuser, output wire m_axis_cq_tlast, output wire [KEEP_WIDTH-1:0] m_axis_cq_tkeep, output wire m_axis_cq_tvalid, input m_axis_cq_tready, //------------------------------------------------------- input [C_DATA_WIDTH-1:0] s_axis_cc_tdata, input [AXI4_CC_TUSER_WIDTH-1:0] s_axis_cc_tuser, input s_axis_cc_tlast, input [KEEP_WIDTH-1:0] s_axis_cc_tkeep, input s_axis_cc_tvalid, output wire [3:0] s_axis_cc_tready, //------------------------------------------------------- // 3. Configuration (CFG) Interface - EP and RP //------------------------------------------------------- output [3:0] pcie_tfc_nph_av, output [3:0] pcie_tfc_npd_av, //------------------------------------------------------- // Error Reporting Interface //------------------------------------------------------- output wire [5:0] pcie_rq_seq_num0, output wire pcie_rq_seq_num_vld0, output wire [5:0] pcie_rq_seq_num1, output wire pcie_rq_seq_num_vld1, output wire [7:0] pcie_rq_tag0, output wire pcie_rq_tag_vld0, output wire [7:0] pcie_rq_tag1, output wire pcie_rq_tag_vld1, output wire [3:0] pcie_rq_tag_av, input [1:0] pcie_cq_np_req, output [5:0] pcie_cq_np_req_count, output cfg_phy_link_down, output [1:0] cfg_phy_link_status, output [2:0] cfg_negotiated_width, output [1:0] cfg_current_speed, output [1:0] cfg_max_payload, output [2:0] cfg_max_read_req, output [15:0] cfg_function_status, output [11:0] cfg_function_power_state, output [503:0] cfg_vf_status, output [755:0] cfg_vf_power_state, output [1:0] cfg_link_power_state, output cfg_err_cor_out, output cfg_err_nonfatal_out, output cfg_err_fatal_out, output [4:0] cfg_local_error_out, output cfg_local_error_valid, output [5:0] cfg_ltssm_state, output [1:0] cfg_rx_pm_state, output [1:0] cfg_tx_pm_state, output [3:0] cfg_rcb_status, output [1:0] cfg_obff_enable, output cfg_pl_status_change, output [3:0] cfg_tph_requester_enable, output [11:0] cfg_tph_st_mode, output [251:0] cfg_vf_tph_requester_enable, output [755:0] cfg_vf_tph_st_mode, //------------------------------------------------------- // Interrupt Interface Signals //------------------------------------------------------- input [3:0] cfg_interrupt_int, input [1:0] cfg_interrupt_pending, output cfg_interrupt_sent, output [3:0] cfg_interrupt_msi_enable, output [11:0] cfg_interrupt_msi_mmenable, output cfg_interrupt_msi_mask_update, output [31:0] cfg_interrupt_msi_data, input [1:0] cfg_interrupt_msi_select, input [31:0] cfg_interrupt_msi_int, input [63:0] cfg_interrupt_msi_pending_status, output cfg_interrupt_msi_sent, output cfg_interrupt_msi_fail, input [2:0] cfg_interrupt_msi_attr, input cfg_interrupt_msi_tph_present, input [1:0] cfg_interrupt_msi_tph_type, input [7:0] cfg_interrupt_msi_tph_st_tag, input cfg_interrupt_msi_pending_status_data_enable, input [3:0] cfg_interrupt_msi_pending_status_function_num, input [2:0] cfg_interrupt_msi_function_number, //------------------------------------------------------- input sys_clk, input sys_clk_gt, input sys_reset_n //------------------------------------------------------- ); //--------------------------------------------------------------------------------------------------------------------// // Connections between Root Port and Configurator //--------------------------------------------------------------------------------------------------------------------// wire [3:0] rport_s_axis_rq_tready; wire [C_DATA_WIDTH-1:0] rport_s_axis_rq_tdata; wire [KEEP_WIDTH-1:0] rport_s_axis_rq_tkeep; wire [AXI4_RQ_TUSER_WIDTH-1:0] rport_s_axis_rq_tuser; wire rport_s_axis_rq_tlast; wire rport_s_axis_rq_tvalid; wire [C_DATA_WIDTH-1:0] rport_m_axis_rc_tdata; wire [KEEP_WIDTH-1:0] rport_m_axis_rc_tkeep; wire rport_m_axis_rc_tlast; wire rport_m_axis_rc_tvalid; wire rport_m_axis_rc_tready; wire [AXI4_RC_TUSER_WIDTH-1:0] rport_m_axis_rc_tuser; // wire cfg_msg_received; // wire [7 : 0] cfg_msg_received_data; // wire [4 : 0] cfg_msg_received_type; // ila_32 ila_cgator_0 ( // .clk(user_clk_out), // .probe0({ // cfg_msg_received, // cfg_msg_received_data, // cfg_msg_received_type // }) // ); //---------------------------------------------------------------------------------------// // Core Top Level Wrapper generate if (PCIE_LOCATION == "X0Y0") begin pcie4_uscale_plus_0 pcie4_uscale_plus_0_i ( //---------------------------------------------------------------------------------------// // PCI Express (pci_exp) Interface // //---------------------------------------------------------------------------------------// //---------------------------------------------------------------------------------------// // PCI Express (pci_exp) Interface // //---------------------------------------------------------------------------------------// // Tx .pci_exp_txn ( pci_exp_txn ), .pci_exp_txp ( pci_exp_txp ), // Rx .pci_exp_rxn ( pci_exp_rxn ), .pci_exp_rxp ( pci_exp_rxp ), //---------------------------------------------------------------------------------------// // AXI Interface // //---------------------------------------------------------------------------------------// .user_clk ( user_clk_out ), .user_reset ( user_reset_out ), .user_lnk_up ( user_lnk_up ), .phy_rdy_out ( phy_rdy_out ), .s_axis_rq_tlast ( rport_s_axis_rq_tlast ), .s_axis_rq_tdata ( rport_s_axis_rq_tdata ), .s_axis_rq_tuser ( rport_s_axis_rq_tuser ), .s_axis_rq_tkeep ( rport_s_axis_rq_tkeep ), .s_axis_rq_tready ( rport_s_axis_rq_tready ), .s_axis_rq_tvalid ( rport_s_axis_rq_tvalid ), .m_axis_rc_tdata ( rport_m_axis_rc_tdata ), .m_axis_rc_tuser ( rport_m_axis_rc_tuser ), .m_axis_rc_tlast ( rport_m_axis_rc_tlast ), .m_axis_rc_tkeep ( rport_m_axis_rc_tkeep ), .m_axis_rc_tvalid ( rport_m_axis_rc_tvalid ), .m_axis_rc_tready ( rport_m_axis_rc_tready ), .m_axis_cq_tdata ( m_axis_cq_tdata ), .m_axis_cq_tuser ( m_axis_cq_tuser ), .m_axis_cq_tlast ( m_axis_cq_tlast ), .m_axis_cq_tkeep ( m_axis_cq_tkeep ), .m_axis_cq_tvalid ( m_axis_cq_tvalid ), .m_axis_cq_tready ( m_axis_cq_tready ), .s_axis_cc_tdata ( s_axis_cc_tdata ), .s_axis_cc_tuser ( s_axis_cc_tuser ), .s_axis_cc_tlast ( s_axis_cc_tlast ), .s_axis_cc_tkeep ( s_axis_cc_tkeep ), .s_axis_cc_tvalid ( s_axis_cc_tvalid ), .s_axis_cc_tready ( s_axis_cc_tready ), //---------------------------------------------------------------------------------------// // Configuration (CFG) Interface // //---------------------------------------------------------------------------------------// .pcie_tfc_nph_av ( pcie_tfc_nph_av ), .pcie_tfc_npd_av ( pcie_tfc_npd_av ), .pcie_rq_seq_num0 ( pcie_rq_seq_num0) , .pcie_rq_seq_num_vld0 ( pcie_rq_seq_num_vld0) , .pcie_rq_seq_num1 ( pcie_rq_seq_num1) , .pcie_rq_seq_num_vld1 ( pcie_rq_seq_num_vld1) , .pcie_rq_tag0 ( pcie_rq_tag0) , .pcie_rq_tag1 ( pcie_rq_tag1) , .pcie_rq_tag_av ( pcie_rq_tag_av) , .pcie_rq_tag_vld0 ( pcie_rq_tag_vld0) , .pcie_rq_tag_vld1 ( pcie_rq_tag_vld1) , .pcie_cq_np_req ( pcie_cq_np_req ), .pcie_cq_np_req_count ( pcie_cq_np_req_count ), .cfg_phy_link_down ( cfg_phy_link_down ), .cfg_phy_link_status ( cfg_phy_link_status), .cfg_negotiated_width ( cfg_negotiated_width ), .cfg_current_speed ( cfg_current_speed ), .cfg_max_payload ( cfg_max_payload ), .cfg_max_read_req ( cfg_max_read_req ), .cfg_function_status ( cfg_function_status ), .cfg_function_power_state ( cfg_function_power_state ), .cfg_vf_status ( cfg_vf_status ), .cfg_vf_power_state ( cfg_vf_power_state ), .cfg_link_power_state ( cfg_link_power_state ), // Error Reporting Interface .cfg_err_cor_out ( cfg_err_cor_out ), .cfg_err_nonfatal_out ( cfg_err_nonfatal_out ), .cfg_err_fatal_out ( cfg_err_fatal_out ), .cfg_local_error_out ( cfg_local_error_out ), .cfg_local_error_valid ( cfg_local_error_valid ), .cfg_ltssm_state ( cfg_ltssm_state ), .cfg_rx_pm_state ( cfg_rx_pm_state ), .cfg_tx_pm_state ( cfg_tx_pm_state ), .cfg_rcb_status ( cfg_rcb_status ), .cfg_obff_enable ( cfg_obff_enable ), .cfg_pl_status_change ( cfg_pl_status_change ), .cfg_tph_requester_enable ( cfg_tph_requester_enable ), .cfg_tph_st_mode ( cfg_tph_st_mode ), .cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ), .cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ), // /* agan add @ 20220603, for debug*/ // .cfg_msg_received ( cfg_msg_received ) , // .cfg_msg_received_data ( cfg_msg_received_data ), // .cfg_msg_received_type ( cfg_msg_received_type ), // // //-------------------------------------------------------------------------------// // EP Only // //-------------------------------------------------------------------------------// // Interrupt Interface Signals .cfg_interrupt_int ( cfg_interrupt_int ), .cfg_interrupt_pending ( {2'b0,cfg_interrupt_pending} ), .cfg_interrupt_sent ( cfg_interrupt_sent ), .cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ), .cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ), .cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ), .cfg_interrupt_msi_data ( cfg_interrupt_msi_data ), .cfg_interrupt_msi_select ( cfg_interrupt_msi_select ), .cfg_interrupt_msi_int ( cfg_interrupt_msi_int ), .cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status [31:0]), .cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ), .cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ), .cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ), .cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ), .cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ), .cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ), .cfg_interrupt_msi_pending_status_function_num (2'b0), .cfg_interrupt_msi_pending_status_data_enable (1'b0), .cfg_interrupt_msi_function_number (8'b0 ), //--------------------------------------------------------------------------------------// // System(SYS) Interface // //--------------------------------------------------------------------------------------// .sys_clk ( sys_clk ), .sys_clk_gt ( sys_clk_gt ), .sys_reset ( sys_reset_n ) ); end else if (PCIE_LOCATION == "X0Y1") begin pcie4_uscale_plus_1 pcie4_uscale_plus_0_i ( //---------------------------------------------------------------------------------------// // PCI Express (pci_exp) Interface // //---------------------------------------------------------------------------------------// //---------------------------------------------------------------------------------------// // PCI Express (pci_exp) Interface // //---------------------------------------------------------------------------------------// // Tx .pci_exp_txn ( pci_exp_txn ), .pci_exp_txp ( pci_exp_txp ), // Rx .pci_exp_rxn ( pci_exp_rxn ), .pci_exp_rxp ( pci_exp_rxp ), //---------------------------------------------------------------------------------------// // AXI Interface // //---------------------------------------------------------------------------------------// .user_clk ( user_clk_out ), .user_reset ( user_reset_out ), .user_lnk_up ( user_lnk_up ), .phy_rdy_out ( phy_rdy_out ), .s_axis_rq_tlast ( rport_s_axis_rq_tlast ), .s_axis_rq_tdata ( rport_s_axis_rq_tdata ), .s_axis_rq_tuser ( rport_s_axis_rq_tuser ), .s_axis_rq_tkeep ( rport_s_axis_rq_tkeep ), .s_axis_rq_tready ( rport_s_axis_rq_tready ), .s_axis_rq_tvalid ( rport_s_axis_rq_tvalid ), .m_axis_rc_tdata ( rport_m_axis_rc_tdata ), .m_axis_rc_tuser ( rport_m_axis_rc_tuser ), .m_axis_rc_tlast ( rport_m_axis_rc_tlast ), .m_axis_rc_tkeep ( rport_m_axis_rc_tkeep ), .m_axis_rc_tvalid ( rport_m_axis_rc_tvalid ), .m_axis_rc_tready ( rport_m_axis_rc_tready ), .m_axis_cq_tdata ( m_axis_cq_tdata ), .m_axis_cq_tuser ( m_axis_cq_tuser ), .m_axis_cq_tlast ( m_axis_cq_tlast ), .m_axis_cq_tkeep ( m_axis_cq_tkeep ), .m_axis_cq_tvalid ( m_axis_cq_tvalid ), .m_axis_cq_tready ( m_axis_cq_tready ), .s_axis_cc_tdata ( s_axis_cc_tdata ), .s_axis_cc_tuser ( s_axis_cc_tuser ), .s_axis_cc_tlast ( s_axis_cc_tlast ), .s_axis_cc_tkeep ( s_axis_cc_tkeep ), .s_axis_cc_tvalid ( s_axis_cc_tvalid ), .s_axis_cc_tready ( s_axis_cc_tready ), //---------------------------------------------------------------------------------------// // Configuration (CFG) Interface // //---------------------------------------------------------------------------------------// .pcie_tfc_nph_av ( pcie_tfc_nph_av ), .pcie_tfc_npd_av ( pcie_tfc_npd_av ), .pcie_rq_seq_num0 ( pcie_rq_seq_num0) , .pcie_rq_seq_num_vld0 ( pcie_rq_seq_num_vld0) , .pcie_rq_seq_num1 ( pcie_rq_seq_num1) , .pcie_rq_seq_num_vld1 ( pcie_rq_seq_num_vld1) , .pcie_rq_tag0 ( pcie_rq_tag0) , .pcie_rq_tag1 ( pcie_rq_tag1) , .pcie_rq_tag_av ( pcie_rq_tag_av) , .pcie_rq_tag_vld0 ( pcie_rq_tag_vld0) , .pcie_rq_tag_vld1 ( pcie_rq_tag_vld1) , .pcie_cq_np_req ( pcie_cq_np_req ), .pcie_cq_np_req_count ( pcie_cq_np_req_count ), .cfg_phy_link_down ( cfg_phy_link_down ), .cfg_phy_link_status ( cfg_phy_link_status), .cfg_negotiated_width ( cfg_negotiated_width ), .cfg_current_speed ( cfg_current_speed ), .cfg_max_payload ( cfg_max_payload ), .cfg_max_read_req ( cfg_max_read_req ), .cfg_function_status ( cfg_function_status ), .cfg_function_power_state ( cfg_function_power_state ), .cfg_vf_status ( cfg_vf_status ), .cfg_vf_power_state ( cfg_vf_power_state ), .cfg_link_power_state ( cfg_link_power_state ), // Error Reporting Interface .cfg_err_cor_out ( cfg_err_cor_out ), .cfg_err_nonfatal_out ( cfg_err_nonfatal_out ), .cfg_err_fatal_out ( cfg_err_fatal_out ), .cfg_local_error_out ( cfg_local_error_out ), .cfg_local_error_valid ( cfg_local_error_valid ), .cfg_ltssm_state ( cfg_ltssm_state ), .cfg_rx_pm_state ( cfg_rx_pm_state ), .cfg_tx_pm_state ( cfg_tx_pm_state ), .cfg_rcb_status ( cfg_rcb_status ), .cfg_obff_enable ( cfg_obff_enable ), .cfg_pl_status_change ( cfg_pl_status_change ), .cfg_tph_requester_enable ( cfg_tph_requester_enable ), .cfg_tph_st_mode ( cfg_tph_st_mode ), .cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ), .cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ), // /* agan add @ 20220603, for debug*/ // .cfg_msg_received ( cfg_msg_received ) , // .cfg_msg_received_data ( cfg_msg_received_data ), // .cfg_msg_received_type ( cfg_msg_received_type ), // // //-------------------------------------------------------------------------------// // EP Only // //-------------------------------------------------------------------------------// // Interrupt Interface Signals .cfg_interrupt_int ( cfg_interrupt_int ), .cfg_interrupt_pending ( {2'b0,cfg_interrupt_pending} ), .cfg_interrupt_sent ( cfg_interrupt_sent ), .cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ), .cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ), .cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ), .cfg_interrupt_msi_data ( cfg_interrupt_msi_data ), .cfg_interrupt_msi_select ( cfg_interrupt_msi_select ), .cfg_interrupt_msi_int ( cfg_interrupt_msi_int ), .cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status [31:0]), .cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ), .cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ), .cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ), .cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ), .cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ), .cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ), .cfg_interrupt_msi_pending_status_function_num (2'b0), .cfg_interrupt_msi_pending_status_data_enable (1'b0), .cfg_interrupt_msi_function_number (8'b0 ), //--------------------------------------------------------------------------------------// // System(SYS) Interface // //--------------------------------------------------------------------------------------// .sys_clk ( sys_clk ), .sys_clk_gt ( sys_clk_gt ), .sys_reset ( sys_reset_n ) ); end endgenerate // IBUF sys_reset_n_ibuf (.O(sys_rst_n_c), .I(sys_reset_n)); //IBUFDS_GTE3 refclk_ibuf (.O(sys_clk_gt), .ODIV2(sys_clk), .I(sys_clk_p), .CEB(1'b0), .IB(sys_clk_n)); //--------------------------------------------------------------------------------------------------------------------// // Instantiate Configurator design //--------------------------------------------------------------------------------------------------------------------// cgator #( .TCQ ( TCQ ), .AXISTEN_IF_RQ_ALIGNMENT_MODE (AXISTEN_IF_RQ_ALIGNMENT_MODE), .EXTRA_PIPELINE ( EXTRA_PIPELINE ), .ROM_SIZE ( ROM_SIZE ), .ROM_FILE ( ROM_FILE ), .REQUESTER_ID ( REQUESTER_ID ), .C_DATA_WIDTH ( C_DATA_WIDTH ), .KEEP_WIDTH ( KEEP_WIDTH ) ) cgator_i ( // globals .user_clk ( user_clk_out ), .reset ( user_reset_out ), // User interface for configuration .start_config ( start_config ), .finished_config ( finished_config ), .failed_config ( failed_config ), // Rport AXIS interfaces .rport_s_axis_rq_tready ( rport_s_axis_rq_tready[0]), .rport_s_axis_rq_tdata ( rport_s_axis_rq_tdata ), .rport_s_axis_rq_tkeep ( rport_s_axis_rq_tkeep ), .rport_s_axis_rq_tuser ( rport_s_axis_rq_tuser ), .rport_s_axis_rq_tlast ( rport_s_axis_rq_tlast ), .rport_s_axis_rq_tvalid ( rport_s_axis_rq_tvalid ), .rport_m_axis_rc_tdata ( rport_m_axis_rc_tdata ), .rport_m_axis_rc_tkeep ( rport_m_axis_rc_tkeep ), .rport_m_axis_rc_tlast ( rport_m_axis_rc_tlast ), .rport_m_axis_rc_tvalid ( rport_m_axis_rc_tvalid ), .rport_m_axis_rc_tready ( rport_m_axis_rc_tready ), .rport_m_axis_rc_tuser ( rport_m_axis_rc_tuser ), // User AXIS interfaces .usr_s_axis_rq_tready ( s_axis_rq_tready ), .usr_s_axis_rq_tdata ( s_axis_rq_tdata ), .usr_s_axis_rq_tkeep ( s_axis_rq_tkeep ), .usr_s_axis_rq_tuser ( s_axis_rq_tuser ), .usr_s_axis_rq_tlast ( s_axis_rq_tlast ), .usr_s_axis_rq_tvalid ( s_axis_rq_tvalid ), .usr_m_axis_rc_tdata ( m_axis_rc_tdata ), .usr_m_axis_rc_tkeep ( m_axis_rc_tkeep ), .usr_m_axis_rc_tlast ( m_axis_rc_tlast ), .usr_m_axis_rc_tvalid ( m_axis_rc_tvalid ), .usr_m_axis_rc_tuser ( m_axis_rc_tuser ), .usr_m_axis_rc_tready ( m_axis_rc_tready ) // Rport CFG interface // User CFG interface // Rport PL interface ); //--------------------------------------------------------------------------------------------------------------------// endmodule // cgator_wrapper 这是cgator_wrapper的文件,ila核应该怎么配置?
08-07
`timescale 1ps / 1ps (* DowngradeIPIdentifiedWarnings = "yes" *) module axi_10g_ethernet_0_example_design ( // Clock inputs input clk_in_p, // Freerunning clock source input clk_in_n, input refclk_p, // Transceiver reference clock source input refclk_n, output coreclk_out, //LED3 // Example design control inputs input pcs_loopback, input reset, input reset_error, input insert_error, input enable_pat_gen, input enable_pat_check, output serialized_stats, //LED5 input sim_speedup_control, input enable_custom_preamble, // Example design status outputs output frame_error, //LED0 output gen_active_flash, //LED2 output check_active_flash, //LED1 output core_ready, //LED7 output qplllock_out, //LED6 // Serial I/O from/to transceiver output txp, output txn, input rxp, input rxn ); /*-------------------------------------------------------------------------*/ // Set FIFO memory size localparam FIFO_SIZE = 1024; // Signal declarations wire enable_vlan; wire reset_error_sync; wire coreclk; wire block_lock; wire rxrecclk; wire s_axi_aclk; wire tx_dcm_locked; wire tx_s_axis_aresetn; wire tx_s_axis_areset; wire [10:0] s_axi_awaddr; wire s_axi_awvalid; wire s_axi_awready; wire [31:0] s_axi_wdata; wire s_axi_wvalid; wire s_axi_wready; wire [1:0] s_axi_bresp; wire s_axi_bvalid; wire s_axi_bready; wire [10:0] s_axi_araddr; wire s_axi_arvalid; wire s_axi_arready; wire [31:0] s_axi_rdata; wire [1:0] s_axi_rresp; wire s_axi_rvalid; wire s_axi_rready; wire enable_gen_after_config; wire enable_gen_synced; wire tx_statistics_vector; wire rx_statistics_vector; wire [25:0] tx_statistics_vector_int; wire tx_statistics_valid_int; reg tx_statistics_valid; reg [27:0] tx_statistics_shift = 0; wire [29:0] rx_statistics_vector_int; wire rx_statistics_valid_int; reg rx_statistics_valid; reg [31:0] rx_statistics_shift = 0; wire [63:0] tx_axis_tdata; wire [7:0] tx_axis_tkeep; wire tx_axis_tvalid; wire tx_axis_tlast; wire tx_axis_tready; wire [63:0] rx_axis_tdata; wire [7:0] rx_axis_tkeep; wire rx_axis_tvalid; wire rx_axis_tlast; wire rx_axis_tready; wire tx_reset; wire rx_reset; wire tx_axis_aresetn; wire rx_axis_aresetn; wire pat_gen_start; wire resetdone_out; wire [7:0] pcspma_status; wire pcs_loopback_sync; wire enable_custom_preamble_sync; wire enable_custom_preamble_coreclk_sync; wire insert_error_sync; assign coreclk_out = coreclk; // Enable or disable VLAN mode assign enable_vlan = 0; // Synchronise example design inputs into the applicable clock domain axi_10g_ethernet_0_sync_block sync_insert_error ( .data_in (insert_error), .clk (coreclk), .data_out (insert_error_sync) ); axi_10g_ethernet_0_sync_block sync_coreclk_enable_custom_preamble ( .data_in (enable_custom_preamble), .clk (coreclk), .data_out (enable_custom_preamble_coreclk_sync) ); axi_10g_ethernet_0_sync_block sync_pcs_loopback ( .data_in (pcs_loopback), .clk (s_axi_aclk), .data_out (pcs_loopback_sync) ); axi_10g_ethernet_0_sync_block sync_enable_custom_preamble ( .data_in (enable_custom_preamble), .clk (s_axi_aclk), .data_out (enable_custom_preamble_sync) ); assign core_ready = block_lock; // Combine reset sources assign tx_axis_aresetn = ~reset & tx_dcm_locked; assign rx_axis_aresetn = ~reset & tx_dcm_locked; assign tx_s_axis_aresetn = ~reset & tx_dcm_locked; assign pat_gen_start = enable_pat_gen ? enable_gen_synced : 0; // The serialized statistics vector output is intended to only prevent logic stripping assign serialized_stats = tx_statistics_vector || rx_statistics_vector; assign tx_reset = reset; assign rx_reset = reset; //-------------------------------------------------------------------------- // Instantiate a module containing the Ethernet core and an example FIFO //-------------------------------------------------------------------------- axi_10g_ethernet_0_fifo_block #( .FIFO_SIZE (FIFO_SIZE) ) fifo_block_i ( .refclk_p (refclk_p), .refclk_n (refclk_n), .coreclk_out (coreclk), .rxrecclk_out (rxrecclk), .dclk (s_axi_aclk), .reset (reset), .tx_ifg_delay (8'd0), .tx_statistics_vector (tx_statistics_vector_int), .tx_statistics_valid (tx_statistics_valid_int), .rx_statistics_vector (rx_statistics_vector_int), .rx_statistics_valid (rx_statistics_valid_int), .pause_val (16'b0), .pause_req (1'b0), .rx_axis_fifo_aresetn (rx_axis_aresetn), .rx_axis_mac_aresetn (rx_axis_aresetn), .rx_axis_fifo_tdata (rx_axis_tdata), .rx_axis_fifo_tkeep (rx_axis_tkeep), .rx_axis_fifo_tvalid (rx_axis_tvalid), .rx_axis_fifo_tlast (rx_axis_tlast), .rx_axis_fifo_tready (rx_axis_tready), .tx_axis_mac_aresetn (tx_axis_aresetn), .tx_axis_fifo_aresetn (tx_axis_aresetn), .tx_axis_fifo_tdata (tx_axis_tdata), .tx_axis_fifo_tkeep (tx_axis_tkeep), .tx_axis_fifo_tvalid (tx_axis_tvalid), .tx_axis_fifo_tlast (tx_axis_tlast), .tx_axis_fifo_tready (tx_axis_tready), .s_axi_aclk (s_axi_aclk), .s_axi_aresetn (tx_s_axis_aresetn), .s_axi_awaddr (s_axi_awaddr), .s_axi_awvalid (s_axi_awvalid), .s_axi_awready (s_axi_awready), .s_axi_wdata (s_axi_wdata), .s_axi_wvalid (s_axi_wvalid), .s_axi_wready (s_axi_wready), .s_axi_bresp (s_axi_bresp), .s_axi_bvalid (s_axi_bvalid), .s_axi_bready (s_axi_bready), .s_axi_araddr (s_axi_araddr), .s_axi_arvalid (s_axi_arvalid), .s_axi_arready (s_axi_arready), .s_axi_rdata (s_axi_rdata), .s_axi_rresp (s_axi_rresp), .s_axi_rvalid (s_axi_rvalid), .s_axi_rready (s_axi_rready), .xgmacint (), .txp (txp), .txn (txn), .rxp (rxp), .rxn (rxn), .signal_detect (1'b1), .tx_fault (1'b0), .sim_speedup_control (sim_speedup_control), .pcspma_status (pcspma_status), .resetdone_out (resetdone_out), .qplllock_out (qplllock_out) ); //-------------------------------------------------------------------------- // Instantiate the AXI-LITE/DRPCLK Clock source module //-------------------------------------------------------------------------- axi_10g_ethernet_0_clocking axi_lite_clocking_i ( .clk_in_p (clk_in_p), .clk_in_n (clk_in_n), .s_axi_aclk (s_axi_aclk), .tx_mmcm_reset (tx_reset), .tx_mmcm_locked (tx_dcm_locked) ); //-------------------------------------------------------------------------- // Instantiate the AXI-LITE Controller //-------------------------------------------------------------------------- axi_10g_ethernet_0_axi_lite_sm axi_lite_controller ( .s_axi_aclk (s_axi_aclk), .s_axi_reset (tx_s_axis_areset), .pcs_loopback (pcs_loopback_sync), .enable_vlan (enable_vlan), .enable_custom_preamble (enable_custom_preamble_sync), .block_lock (block_lock), .enable_gen (enable_gen_after_config), .s_axi_awaddr (s_axi_awaddr), .s_axi_awvalid (s_axi_awvalid), .s_axi_awready (s_axi_awready), .s_axi_wdata (s_axi_wdata), .s_axi_wvalid (s_axi_wvalid), .s_axi_wready (s_axi_wready), .s_axi_bresp (s_axi_bresp), .s_axi_bvalid (s_axi_bvalid), .s_axi_bready (s_axi_bready), .s_axi_araddr (s_axi_araddr), .s_axi_arvalid (s_axi_arvalid), .s_axi_arready (s_axi_arready), .s_axi_rdata (s_axi_rdata), .s_axi_rresp (s_axi_rresp), .s_axi_rvalid (s_axi_rvalid), .s_axi_rready (s_axi_rready) ); //-------------------------------------------------------------------------- // Add reset synchronizers to the asynchronous reset inputs //-------------------------------------------------------------------------- axi_10g_ethernet_0_sync_reset tx_s_axis_reset_gen ( .clk (s_axi_aclk), .reset_in (~tx_s_axis_aresetn), .reset_out (tx_s_axis_areset) ); axi_10g_ethernet_0_sync_block gen_enable_sync ( .clk (coreclk), .data_in (enable_gen_after_config), .data_out (enable_gen_synced) ); axi_10g_ethernet_0_sync_block reset_error_sync_reg ( .clk (coreclk), .data_in (reset_error), .data_out (reset_error_sync) ); //-------------------------------------------------------------------------- // Instantiate the pattern generator / pattern checker and loopback module //-------------------------------------------------------------------------- axi_10g_ethernet_0_gen_check_wrapper pattern_generator ( .dest_addr (48'hda0102030405), .src_addr (48'h5a0102030405), .max_size (15'd300), .min_size (15'd066), .enable_vlan (enable_vlan), .vlan_id (12'h002), .vlan_priority (3'b010), .preamble_data (56'hD55555567555FB), .enable_custom_preamble (enable_custom_preamble_coreclk_sync), .aclk (coreclk), .aresetn (tx_axis_aresetn), .enable_pat_gen (pat_gen_start), .reset_error (reset_error_sync), .insert_error (insert_error_sync), .enable_pat_check (enable_pat_check), .enable_loopback (!pat_gen_start), .frame_error (frame_error), .gen_active_flash (gen_active_flash), .check_active_flash (check_active_flash), .tx_axis_tdata (tx_axis_tdata), .tx_axis_tkeep (tx_axis_tkeep), .tx_axis_tvalid (tx_axis_tvalid), .tx_axis_tlast (tx_axis_tlast), .tx_axis_tready (tx_axis_tready), .rx_axis_tdata (rx_axis_tdata), .rx_axis_tkeep (rx_axis_tkeep), .rx_axis_tvalid (rx_axis_tvalid), .rx_axis_tlast (rx_axis_tlast), .rx_axis_tready (rx_axis_tready) ); //-------------------------------------------------------------------------- // serialise the stats vector output to ensure logic isn't stripped during // synthesis and to reduce the IO required by the example design //-------------------------------------------------------------------------- always @(posedge coreclk) begin tx_statistics_valid <= tx_statistics_valid_int; if (tx_statistics_valid_int & !tx_statistics_valid) begin tx_statistics_shift <= {2'b01,tx_statistics_vector_int}; end else begin tx_statistics_shift <= {tx_statistics_shift[26:0], 1'b0}; end end assign tx_statistics_vector = tx_statistics_shift[27]; always @(posedge coreclk) begin rx_statistics_valid <= rx_statistics_valid_int; if (rx_statistics_valid_int & !rx_statistics_valid) begin rx_statistics_shift <= {2'b01, rx_statistics_vector_int}; end else begin rx_statistics_shift <= {rx_statistics_shift[30:0], 1'b0}; end end assign rx_statistics_vector = rx_statistics_shift[31]; endmodule 分析这段代码的功能,以及举出代码中的子模块
11-22
**代码概述** 该程序从键盘输入一个字符串,判断该字符串是否为“回文串”(忽略首尾空格),若是则输出 `YES`,否则输出 `NO`。但当前代码不完整,存在多处语法错误和缺失。 --- **代码解析** 原始代码中存在明显错误和占位符(如换行、分号错位等),我们先进行修正并还原逻辑: ```c #include <stdio.h> #include <string.h> int main(void) { char ch, s[80], *p, *q; int i, j, n; gets(s); // 输入字符串(不安全,但题目如此) p = s; // p 指向字符串开头 while (*p == ' ') { p++; // 跳过开头的空格 } n = strlen(s); q = s + n - 1; // q 指向字符串最后一个字符 while (*q == ' ') { q--; // 跳过末尾的空格 } while (p < q && *p == *q) { // 从两端向中间比较 p++; q--; } if (p < q) { printf("NO\n"); // 不对称 } else { printf("YES\n"); // 是回文 } return 0; } ``` --- **原题问题分析** 原代码中的空白需要补全: 1. `p = s[0];` 错误!应为指针赋值地址,改为: → `p = s;` 或 `p = &s[0];` 2. 跳过前导空格: ```c while (*p == ' ') { p++; } ``` 3. 设置 `q` 指向末尾非空格字符: → `q = s + n - 1;` 4. 跳过尾部空格: ```c while (*q == ' ') { q--; } ``` 5. 中心循环比较: ```c while (p < q && *p == *q) { p++; q--; } ``` --- **知识点** 1. **指针操作字符串** `$p$ 和 $q$ 可指向字符串两端,通过 $*p++$、$*q--$ 移动。 2. **字符串去空格处理** 忽略首尾空格时,用指针前后扫描跳过。 3. **回文判断逻辑** 从两边向中心推进,若所有对应字符相等,则为回文。
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