仿真报错:Quartus_FPGA/Waveform.vwf specified with --testbench_vector_input_file option does not exist

在使用Quartus进行功能仿真时,若遇到保存.vwf文件的错误,只需使用默认路径和文件名即可避免。若需自定义路径或文件名,可参考特定教程,但每次仿真可能需重新设置,较为繁琐。

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使用Quartus仿真的时候报错:
在这里插入图片描述
解决办法很简单:再点击Run Functional Simulation时会弹出窗口让你保存.vwf仿真文件。在保存.vwf仿真文件的时候用默认的路径和默认的文件名(不要自己修改)就不会报错了。
(当然如果你执意要修改这些,不想用默认的,也有办法。请参考这个帖:https://blog.youkuaiyun.com/a154299/article/details/82912863
不过稍微有麻烦,而且好像每次仿真都要重新修改目录和文件名,浪费时间,所以推荐用默认的吧)

Determining the location of the ModelSim executable... Using: c:/intelfpga_lite/18.1/modelsim_ase/win32aloem/ To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. **** Generating the ModelSim Testbench **** quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jiantongdeng1 -c jiantongdeng1 --vector_source="C:/intelFPGA_lite/18.1/Waveform.vwf" --testbench_file="C:/intelFPGA_lite/18.1/simulation/qsim/Waveform.vwf.vt" Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition Info: Copyright (C) 2018 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Tue Jul 01 16:50:48 2025 Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jiantongdeng1 -c jiantongdeng1 --vector_source=C:/intelFPGA_lite/18.1/Waveform.vwf --testbench_file=C:/intelFPGA_lite/18.1/simulation/qsim/Waveform.vwf.vt Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Error (199014): Vector source file C:/intelFPGA_lite/18.1/Waveform.vwf specified with --testbench_vector_input_file option does not exist Error: Quartus Prime EDA Netlist Writer was unsuccessful. 1 error, 1 warning Error: Peak virtual memory: 4612 megabytes Error: Processing ended: Tue Jul 01 16:50:49 2025 Error: Elapsed time: 00:00:01 Error: Total CPU time (on all processors): 00:00:01 Error.
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07-02
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