这里写自定义目录标题
- 编译Vivado仿真库报错
- Warning: (vlog-159) Mode option -64 is not supported in this context and will be ignored.
- # ** Warning: (vsim-8683) Uninitialized out port /tb_ip_fft2/u_top/u_ip_fft/u_xfft_0/U0///(0) has no driver.
- # Block Memory Generator module tb_ip_fft2.u_top.u_ip_ram.u_ram.inst.native_mem_module.blk_mem_gen_v8_4_2_inst is using a behavioral model for simulation which will not precisely model memory collision behavior.
- xil_defaultlib中包含未知模块
- Break in file E:/Program_Files/Xilinx/Vivado/2018.3/data/ip/xilinx/axi_utils_v2_0/hdl/axi_utils_v2_0_vh_rfs.vhd
编译Vivado仿真库报错
原因是Modelsim版本和Vivado版本不匹配,更换版本之后,只有个别IP报错,不影响使用。
68324 - Vivado Simulation - Supported Third party simulators for major Vivado Design Suite release
我是10.6c+2018.3
Warning: (vlog-159) Mode option -64 is not supported in this context and will be ignored.
这个警告一直没啥影响,所以也没有管它,可能就是设置一个选项的事。
或者说是编译仿真库的时候的一个选项
launch_simulation -install_path E:/Program_Files/modelsim_dlx64_10.6c/win64pe
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'ModelSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in 'F:/MyTest/FPGA/IPFFT2/IPFFT2.sim/sim_1/behav/modelsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [USF-ModelSim-47] Finding simulator installation...
INFO: [USF-ModelSim-50] Using simulator executables from 'E:/Program_Files/modelsim_dlx64_10.6c/win64pe/vsim.exe'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-modelsim-7] Finding pre-compiled libraries...
INFO: [USF-modelsim-11] File 'E:/Program_Files/Xilinx/Modelsim_Vivado_Lib/modelsim.ini' copied to run dir:'F:/MyTest/FPGA/IPFFT2/IPFFT2.sim/sim_1/behav/modelsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_ip_fft2' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported 'F:/MyTest/FPGA/IPFFT2/IPFFT2.sim/sim_1/behav/modelsim/blk_mem_gen_1.mif'
INFO: [SIM-utils-43] Exported 'F:/MyTest/FPGA/IPFFT2/IPFFT2.sim/sim_1/behav/modelsim/tran_matrix_para_1024.coe'
INFO: [SIM-utils-43] Exported 'F:/MyTest/FPGA/IPFFT2/IPFFT2.sim/sim_1/behav/modelsim/bmg_rom.mif'
INFO: [SIM-utils-43] Exported 'F:/MyTest/FPGA/IPFFT2/IPFFT2.sim/sim_1/behav/modelsim/fftshift_1024.coe'
INFO: [USF-ModelSim-107] Finding global include files...
INFO: [USF-ModelSim-108] Finding include directories and verilog header directory paths...
INFO: [USF-ModelSim-109] Fetching design files from 'sim_1'...
INFO: [USF-ModelSim-2] ModelSim::Compile design
INFO: [USF-ModelSim-15] Creating automatic 'do' files...
INFO: [USF-Mode

本文档记录了在使用Vivado进行仿真库编译时遇到的错误和警告,包括Modelsim版本与Vivado版本不匹配、vlog-159警告、未初始化的输出端口警告以及BlockMemoryGenerator模块的行为级模拟警告。大部分问题通过更新Modelsim版本或忽略特定警告已解决,部分IP未综合完整导致的未知模块警告则需检查复位信号。
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